Array of optoelectronic structures and fabrication thereof

Patent metadata

Field	Value
Publication number	US-9923022-B2
Application number	US-201615200753-A
Country	US
Kind code	B2
Filing date	Jul 1, 2016
Priority date	Jul 1, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A method of fabrication of an array of optoelectronic structures. The method first provides a crystalline substrate having cells corresponding to individual optoelectronic structures to be obtained. Each of the cells comprises an opening to the substrate. Then, several first layer portions of a first compound semiconductor material are grown in each the opening to at least partly fill a respective one of the cells and form an essentially planar film portion therein. Next, several second layer portions of a second compound semiconductor material are grown over the first layer portionsthat coalesce to form a coalescent film extending over the first layer portions. Finally, excess portions of materials are removed, to obtain the array of optoelectronic structures. Each optoelectronic structure comprises a stack protruding from the substrate of: a residual portion of one of the second layer portions; and a residual portion of one of the first layer portions.

First claim

What is claimed is:

1. A method of fabrication of an array of optoelectronic structures, comprising:
providing a crystalline substrate with a template structure thereon, wherein the template structure comprises cells corresponding to individual optoelectronic structures to be obtained, each of the cells comprising an opening to the substrate;
growing several first layer portions of a first compound semiconductor material from seeds in each said opening, for each of said first layer portions to a least partly fill a respective one of the cells and form an essentially planar film portion therein;
growing several, second layer portions of a second compound semiconductor material over said first layer portions, for neighboring ones of said second layer portions to coalesce and thereby form a coalescent film extending over said first layer portions; and
removing excess portions of materials extending over one or more portions of the substrate corresponding to lateral boundaries of the cells, wherein each of the optoelectronic structures comprises a stack of: a residual portion of one of said second layer portions; a residual portion of one of said first layer portions; and one or more lower portions of the template structure, said lower portions extending parallel to a surface of the substrate and in mechanical contact therewith, the stack protruding from the substrate.

2. The method of fabrication according to claim 1 , wherein
growing said second layer portions is performed so as for said neighboring ones of said second layer portions to coalesce over the lateral boundaries of the cells and form defective regions over said lateral boundaries.

3. The method of fabrication according to claim 1 , wherein
said lateral boundaries are defined by walls of the template structure, wherein said walls extend perpendicularly to said surface of the substrate,

and wherein,
growing the first layer portions is performed so as for said first layer portions to reach said walls, which form gaps between neighboring ones of the first layer portions grown.

4. The method of fabrication according to claim 1 , wherein:
growing the first layer portions is performed so as for neighboring ones of the first layer portions to coalesce over said lateral boundaries of the cells and form a first coalesced film with first defective regions over said lateral boundaries;
and growing said second layer portions is performed so as for said neighboring ones of said second layer portions to coalesce and form a second coalescent film extending over said first coalesced film and comprising second defective regions over said first defective regions.

5. The method of fabrication according to claim 1 , further comprising, while or after removing said excess portions,
removing, at least partly, the one or more lower portions and/or one or more walls of the template structure, wherein said walls extend perpendicularly to said surface of the substrate.

6. The method of fabrication according to claim 1 , further comprising, after growing said first layer portions and prior to growing said second layer portions,
removing upper portions of the template structure to expose said first layer portions of first compound semiconductor material.

7. The method of fabrication according to claim 1 , wherein
growing said first layer portions comprises: growing said first layer portions perpendicularly to said surface of the substrate and then further growing said first layer portions parallel to said surface of the substrate.

8. The method of fabrication according to claim 1 , wherein
the crystalline substrate provided comprises one or more fiducial markers, the latter arranged at known relative positions from the template structure,

and wherein,
removing said excess portions is performed according to said fiducial markers.

9. The method of fabrication according to claim 1 , wherein
said coalescent film is obtained as a blanket overgrowth.

10. The method of fabrication according to claim 9 , further comprising:
structuring an outermost one of said additional planar films to partly expose a film underneath.

11. The method of fabrication according to claim 1 , further comprising, after growing said second layer portions,
obtaining one or more additional films of respective compound semiconductor materials, extending over said coalescent film,

and wherein,
removing excess portions comprises removing material portions of each of the first, the second and said respective compound semiconductor materials over said lateral boundaries of the cells.

12. The method of fabrication according to claim 1 , wherein
said first compound semiconductor material comprises a binary III-V semiconductor material and said coalescent film comprises one or more of: a binary III-V semiconductor material, a ternary III-V semiconductor material; and a quaternary III-V semiconductor material.

13. The method of fabrication according to claim 1 , wherein
the method further comprises joining the substrate to another substrate.

14. An optoelectronic device comprising an array of optoelectronic structures as obtained according to the method of claim 1 .

15. The optoelectronic device according to claim 14 , wherein
at least a subset of the optoelectronic structures are configured, each, as a photodetector.

16. The optoelectronic device according to claim 15 , wherein
at least a subset of the optoelectronic structures are configured, each, as a semiconductor laser.

17. The optoelectronic device according to claim 14 , wherein
at least a subset of the optoelectronic structures are configured, each, as a light-emitting device.

18. A method of fabrication an array of optoelectronic structures, comprising:
providing a crystalline substrate with a template structure thereon, wherein the template structure comprises cells corresponding to individual optoelectronic structures to be obtained, each of the cells comprising an opening to the substrate;
growing several first layer portions of a first compound semiconductor material from seeds in each said opening, for each of said first layer portions to a least partly fill a respective one of the cells and form an essentially planar film portion therein;
growing several, second layer portions of a second compound semiconductor material over said first layer portions, for neighboring ones of said second layer portions to coalesce and thereby form a coalescent film extending over said first layer portions; and
removing excess portions of materials extending over one or more portions of the substrate corresponding to lateral boundaries of the cells, wherein each of the optoelectronic structures comprises a stack of: a residual portion of one of said second layer portions; and a residual portion of one of said first layer portions, the stack protruding from the substrate,
wherein the substrate provided is a CMOS-fabricated substrate that comprises wires integrated in the substrate, wherein at least some of the wires are arranged so as to be in electrical contact with the one or more lower portions of the template structure.

19. The method of fabrication according to claim 18 , wherein
the method further comprises fabricating electrical conductors connecting, each, a residual portion of one of said second layer portions to one of the wires integrated in the substrate.

Assignees

• IBM

Inventors

• Borg Mattias B
• Czornomaz Lukas
• Deshpande Veeresh V
• Djara Vladimir
• Riel Heike E
• Schmid Heinz

Classifications

• H01S5/4025

  Array arrangements, e.g. constituted by discrete laser diodes or laser bar (H01S5/42 takes precedence) · CPC title

• H01S5/0262

  Photo-diodes, e.g. transceiver devices, bidirectional devices (H01S5/0265 takes precedence) · CPC title

• H01S5/3013

  AIIIBV compounds · CPC title

• H01S5/021

  Silicon based substrates · CPC title

• H01L27/1469 Primary

  Electricity · mapped topic