Support for long channel length nanowire transistors

Patent metadata

Field	Value
Publication number	US-9922942-B2
Application number	US-201615354142-A
Country	US
Kind code	B2
Filing date	Nov 17, 2016
Priority date	Jul 13, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

First claim

The invention claimed is:

1. A method for supporting a nanowire device channel, comprising:
connecting a semiconductor source to a semiconductor drain using at least one nanowire as a device channel, wherein a first end of each of the at least one nanowire is electrically connected to the semiconductor source by a via and a second end of each of the at least one nanowire is connected to the semiconductor drain by a via; and supporting each of the at least one nanowire with an anchor pad integrally formed with this nanowire, wherein the anchor pad is disposed along the span with a distance from the semiconductor source or the semiconductor drain of about 200 nm to form nanowire segments.

2. The method of claim 1 , wherein the nanowire segments are suspended over a substrate on which the source and drain are formed.

3. The method as recited in claim 1 , wherein supporting the at least one nanowire with an anchor pad includes supporting the at least one nanowire with a plurality of anchor pads disposed along the span with a periodicity of about 200 nm.

4. The method of claim 3 , further comprising forming a dielectric layer over the plurality of anchor pads.

5. The method of claim 3 , wherein each of the plurality of anchor pads has a thickness in the range of about 50 nm to about 500 nm.

6. The method of claim 1 , wherein the at least one nanowire is formed by a lithographic process including patterning, and a release etch, that frees the nanowire segments of the at least one nanowire from the substrate.

7. The method of claim 1 , wherein a plurality of nanowires connect the source to the drain.

8. The method of claim 1 , wherein the at least one nanowire has a length in the range of about 500 nm to 2 microns.

9. The method of claim 8 , wherein the at least one nanowire includes nanowire segments having a length in the range of about 50 nm to about 300 nm.

10. The method of claim 9 , wherein a plurality of anchor pads support the at least one nanowire, and the plurality of anchor pads are disposed along, the device channel with a periodicity equal to the nanowire segments length, such that each of the plurality of nanowire segments is supported by at least one anchor pad.

11. A method of forming a nanowire device, comprising:
forming at least one nanowire, including a plurality of integrally formed anchor pads and a plurality of nanowire segments along a span of the at least one nanowire, where the at least one nanowire is configured to connect a semiconductor source of the nanowire device to a semiconductor drain of the nanowire device by attaching one end of the at least one nanowire to the semiconductor source and attaching another end of the at least one nanowire to the semiconductor drain, and where the plurality of integrally formed anchor pads are disposed along the span with a periodicity of about 200 nm and are configured to support the plurality of nanowire segments along the span to prevent sagging.

12. The method of claim 11 , wherein at least a first integrally formed anchor pad has a first size and at least a second anchor pad has a second size different than the first anchor pad size.

13. The method of claim 11 , wherein a plurality of nanowires connects the semiconductor source of the nanowire device to the semiconductor drain, and at least one of the plurality of nanowire segments has a first length different from a second length of another nanowire segment.

14. The method of claim 13 , wherein at least one of the integrally formed anchor pads is placed a distance from the semiconductor source or the semiconductor drain equal to the first length of the at least one of the plurality of nanowire segments.

15. The method of claim 13 , wherein the plurality of nanowire segments has a square cross-section.

16. The method of claim 13 , wherein each of the plurality of nanowire segments is surrounded by a high-K dielectric material.

17. A method of forming a nanowire device, comprising: forming a semiconductor source and a semiconductor drain on a substrate, where the semiconductor source and semiconductor drain are separated by a span; forming at least one nanowire configured to connect the semiconductor source and the semiconductor drain as a device channel, wherein one end of the at least one nanowire is attached to the semiconductor source and the opposite end of the at least nanowire is attached to the semiconductor drain, and wherein the at least one nanowire includes a plurality of integrally formed anchor pads disposed along the length of the at least one nanowire with a periodicity of about 200 nm and configured to support the at least one nanowire from sagging.

18. The method of claim 17 , wherein the at least one nanowire includes a plurality of nanowire segments having a circular cross-section with a diameter between about 5 nm and about 100 nm.

19. The method of claim 17 , wherein each of the plurality of integrally formed anchor pads has a thickness in the range of about 50 nm to about 500 nm.

20. The method of claim 17 , wherein each of the plurality of integrally formed anchor pads has a width in the range of about 20 nm to about 50 nm.

Assignees

• IBM

Inventors

• Balakrishnan Karthik
• Lauer Isaac
• Yamashita Tenko
• Sleight Jeffrey W

Classifications

• H10P14/3462

  Nanowires · CPC title

• H10P14/2914

  Oxides · CPC title

• H10W42/121 Primary

  protecting against mechanical damage (H10W76/00, H10W74/00 take precedence) · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/66477

  Electricity · mapped topic