General four-port on-wafer high frequency de-embedding method

Patent metadata

Field	Value
Publication number	US-9922888-B2
Application number	US-201615143921-A
Country	US
Kind code	B2
Filing date	May 2, 2016
Priority date	Mar 30, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

The present invention provides a general four-port on-wafer high frequency de-embedding method. The method comprises: for each on-wafer de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the on-wafer de-embedding dummy; obtaining the intrinsic Y-parameter admittance matrix of said N on-wafer de-embedding dummies by calculation or simulation by using said models; and solving the equation set which the corresponding measurement and calculation or simulation data of said on-wafer de-embedding dummies satisfy for the elements of the related admittance matrices of the parasitic four-port network to be stripped in de-embedding and model parameters of models on which said calculation or simulation is based.

First claim

The invention claimed is:

1. A general four-port on-wafer high frequency de-embedding method, comprising the following steps:
1.1: fabricating, together with a device under test (DUT) to be de-embedded, N on-wafer de-embedding dummies;
1.2: measuring to obtain the whole Y-parameter admittance matrix Y M of said DUT and the whole Y-parameter admittance matrix Y Mj (j=1,2, . . . , N) of each of said de-embedding dummies;
1.3: for each de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the de-embedding dummy;
1.4: obtaining the intrinsic Y-parameter admittance matrix Y Aj (p 1 , p 2 , . . . p M ) (j=1,2, . . . , N) of said N de-embedding dummies by calculation or simulation by using said models,
where, p 1 , p 2 , . . . , p M are M model parameters of models on which said calculation or simulation is based, and 4N−16≥M;
1.5: solving an equation set Y Mj =Y ee −Y ei (Y Aj (p 1 , p 2 , . . . p M )+Y ii ) −1 Y ie (j=1,2, . . . , N) for the elements of four sub-matrices Y ee , Y ii , Y ei and Y ie of the admittance matrix Y of the parasitic four-port network to be stripped in de-embedding and said model parameters p 1 , p 2 , . . . , p M as unknowns,
wherein, as shown in the following equation, Y ee , Y ii , Y ei and Y ie as four sub-matrices, form an admittance matrix Y of said parasitic four-port network:

Y
=

[

Y
ee

Y
ei

Y
ie

Y
ii

]

;

and
1.6: substituting Y ee , Y ii , Y ei and Y ie obtained in Step 1.5 and the whole Y-parameter admittance matrix Y M of said DUT obtained by measurement in Step 1.2 into Equation Y A =Y ii −Y ie (Y M −Y ee ) −1 Y ei , to obtain by calculation the intrinsic Y-parameter admittance matrix Y A of said DUT.

2. The general four-port on-wafer high frequency de-embedding method according to claim 1 , characterized in that solving the equation set Y Mj =Y ee −Y ei (Y Aj (p 1 , p 2 , . . . p M )+Y ii ) −1 Y ie (j=1,2, . . . , N) for the elements of four sub-matrixes Y ee , Y ii , Y ei and Y ie of the admittance matrix Y of the parasitic four-port network to be stripped in de-embedding and said model parameters p 1 , p 2 , . . . , p M as unknowns in Step 1.5 comprises the following steps:
2.1: assigning initial values to said model parameters p 1 , p 2 , . . . p M , respectively;
2.2: obtaining the values of Y Aj (p 1 , p 2 , . . . p M )(j=1,2, . . . , N) by calculation or simulation by using the assigned model parameters p 1 , p 2 , . . . p M ;
2.3: after solving an equation set Y Mj =Y ee −Y ei (Y Aj (p 1 , p 2 , . . . p M )+Y ii ) −1 Y ie (j=1,2,3,4) by using the known measurement values Y Mj (j=1,2,3,4) of the first four de-embedding dummies and said calculated or simulated values Y Aj (p 1 , p 2 , . . . p M )(j=1,2,3,4) to obtain the values of Y ee , Y ii , Y ei and Y ie , substituting the known measurement values Y Mj (j=5,6, . . . , N) of the remaining de-embedding dummies and said obtained values of Y ee , Y ii , Y ei and Y ie into Y Dj =−Y ii −Y ie (Y Mj −Y ee ) −1 Y ei (j=5,6, . . . , N) to obtain by calculation the de-embedded Y-parameter admittance matrix Y Dj (j=5,6, . . . , N) of said remaining de-embedding dummies;
2.4: comparing the calculated Y Dj (j=5,6, . . . , N) with the calculated or simulated values Y Aj (p 1 , p 2 , . . . p M )(j=5,6, . . . , N) of the corresponding remaining de-embedding dummies already obtained in Step 2.1,
determining final values for undetermined model parameters p 1 , p 2 , . . . p M which are necessary for the calculation or simulation of the de-embedding dummies, if a difference between the two meets the set error standard, and
correcting the values of the model parameters p 1 , p 2 , . . . p M and reassigning them, and then turning back to Step 2.2, if the difference between the two does not meet the set error standard.

3. A general four-port on-wafer high frequency de-embedding method of passivity, reciprocity and symmetry, comprising the following steps:
3.1: fabricating, together with a device under test (DUT) to be de-embedded, N de-embedding dummies of passivity, reciprocity and symmetry;
3.2: measuring to obtain the whole Y-parameter admittance matrix Y M of said DUT and the whole Y-parameter admittance matrix Y Mj (j=1,2, . . . , N) of each of said de-embedding dummies;
3.3: for each de-embedding dummy, building a model considering the distributive nature of high frequency characteristics of the de-embedding dummy;
3.4: obtaining the intrinsic Y-parameter admittance matrices Y Aj (p 1 , p 2 , . . . p M )(j=1,2, . . . , N) of said N de-embedding dummies by calculation or simulation by using said models,
where, p 1 , p 2 , . . . , p M are M model parameters of models on which said calculation or simulation is based, and 2N−6≥M;
3.5: solving an equation set Y Mj =Y ee −Y ei (Y Aj (p 1 , p 2 , . . . p M )+Y ii ) −1 Y ei (j=1,2, . . . , N) for the elements of three sub-matrices Y ee , Y ii and Y ei of the admittance matrix Y of the parasitic four-port network to be stripped in de-embedding and said model parameters p 1 , p 2 , . . . , p M as unknowns,
wherein, as shown in the following equation, Y ee , Y ii and Y ei , as three sub-matrices, form the admittance matrix Y of said parasitic four-port network:

Y
=

[

Y
ee

Y
ei

Y
ei

Y
ii

]

;

and
3.6: substituting Y ee , Y ii and Y ei obtained in Step 3.5 and the whole Y-parameter admittance matrix Y M of said DUT obtained by measurement in Step 3.2 into Equation Y A =−Y ii −Y ei (Y M −Y ee ) −1 Y ei , to obtain by calculation the intrinsic Y-parameter admittance matrix Y A of said DUT.

4. The special general four-port on-wafer high frequency de-embedding method according to claim 3 , characterized in that solving the equation set Y Mj =Y ee −Y ei (Y Aj (p 1 , p 2 , . . . p M )+Y ii ) −1 Y ei (j=1,2, . . . , N for the elements of three sub-matri

Assignees

• Univ Tsinghua

Inventors

• Fu Jun
• Wang yu-dong
• Cui Jie
• Zhao Yue
• Cui wen-pu
• Liu zhi-hong

Classifications

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/207 Primary

  Electrical properties, e.g. testing or measuring of resistance, deep levels or capacitance-voltage characteristics · CPC title

• H01L22/14 Primary

  Electricity · mapped topic

• G01R27/2623

  Measuring-systems or electronic circuits (G01R27/2635, G01R27/2682 take precedence) · CPC title