Method of manufacturing semiconductor package

Patent metadata

Field	Value
Publication number	US-9922846-B2
Application number	US-201615286828-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Oct 7, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A method of manufacturing a semiconductor package includes preparing a package substrate including a semiconductor chip mounting region. A semiconductor chip is mounted in the semiconductor chip mounting region. A dam surrounding the semiconductor chip is formed. The formation of the dam includes depositing a first solution having a temperature below a set first temperature. A region under the semiconductor chip and a region defined by the dam are filled with an underfill by depositing the first solution having a temperature equal to or higher than the set first temperature.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor package, the method comprising:
preparing a package substrate including a semiconductor chip mounting region;
mounting a semiconductor chip in the semiconductor chip mounting region;
forming a dam surrounding the semiconductor chip by depositing a first solution having a temperature below a set first temperature; and
filling a region under the semiconductor chip and a region defined by the dam with an underfill by depositing the first solution having a temperature equal to or higher than the set first temperature.

2. The method of claim 1 , wherein the set first temperature is a temperature having a value in the range from about 40° C. to about 50° C.

3. The method of claim 2 , wherein a viscosity of the first solution used for forming the dam at the temperature below the set temperature is higher than a viscosity of the first solution used for filling the region under the semiconductor chip and the region defined by the dam with the underfill at a temperature equal to or higher than the set first temperature.

4. The method of claim 1 , wherein the first solution is deposited via a nozzle, and
a diameter of a first nozzle configured to deposit the first solution at the temperature below the set first temperature is smaller than a diameter of a second nozzle configured to deposit the first solution at the temperature equal to or higher than the set first temperature.

5. The method of claim 4 , wherein a start point of the dam contacts an end point of the dam.

6. The method of claim 4 , wherein a plurality of second nozzles are provided, and the method further comprises simultaneously depositing the first solution via at least one of the plurality of second nozzles.

7. The method of claim 6 , wherein the method comprises depositing the first solution between the semiconductor chip and the dam via at least one of the plurality of second nozzles, and depositing the first solution between the semiconductor chips via the remaining second nozzles.

8. The method of claim 1 , wherein the dam is spaced apart from the semiconductor chip.

9. The method of claim 1 , further comprising, after the filling of the region under the semiconductor chip and the region defined by the dam with the underfill, curing the dam and the underfill.

10. The method of claim 9 , wherein the curing of the dam and the underfill comprises applying a constant second temperature to the dam and the underfill simultaneously.

11. The method of claim 10 , wherein the constant second temperature has a value in a range from about 60° C. to about 80° C.

12. The method of claim 1 , wherein the viscosity of the first solution is inversely proportional to the temperature of the first solution when the temperature of the first solution ranges from about 30° C. and about 70° C.

13. The method of claim 12 , wherein, when the set first temperature is about 40° C. and the temperature of first solution is between about 39° C. and about 30° C., the viscosity of the first solution is a value that ranges from about 1571.5 mPa s to about 2125 mPa·s.

14. The method of claim 1 , wherein the first solution includes about 40% by weight epoxy resin and about 10% by weight silicone.

15. A method of manufacturing a semiconductor package, the method comprising:
preparing a package substrate having a semiconductor chip mounting region, the package substrate including a substrate pad formed inside of the semiconductor chip mounting region of the package substrate;
forming a dam to surround the semiconductor chip mounting region, wherein the forming of the dam includes using a first solution while a viscosity of the first solution is equal to or higher than a set first viscosity;
mounting a semiconductor chip in the semiconductor chip mounting region, wherein the mounting of the semiconductor chip includes electrically connecting the semiconductor chip to the substrate pad; and
filling a region under the semiconductor chip and a region defined by the dam with an underfill by using the first solution while the viscosity of the first solution is below the set first viscosity.

16. The method of claim 15 , wherein the set first viscosity has a value in a range from about 1000 mPa·s to about 1500 mPa·s, and
the viscosity of the first solution varies according to temperature.

17. The method of claim 16 , wherein the first solution comprises a material containing at least one selected from the group consisting of an epoxy resin, a phenol resin, and a silicone-based material.

18. The method of claim 15 , wherein the dam comprises at least one closed curve.

19. The method of claim 18 , wherein the filling of the region under the semiconductor chip and the region defined by the dam with the underfill comprises filling the at least one closed curve with the underfill.

20. The method of claim 15 , further comprising simultaneously curing the dam and the underfill by applying a constant temperature.

21. The method of claim 15 , further comprising:
forming the dam surrounding the semiconductor chip by using the first solution having a temperature below a set first temperature; and
filling the region under the semiconductor chip and a region defined by the dam with the underfill by using the first solution having a temperature equal to or higher than the set first temperature.

22. A method of manufacturing a semiconductor package, the method comprising:
preparing a package substrate having a semiconductor chip mounting region, the package substrate including a substrate pad formed inside of the semiconductor chip mounting region of the package substrate;
forming a raised portion to surround the semiconductor chip mounting region, wherein the forming of the raised portion includes depositing a first solution while a temperature of the first solution is lower than a set first temperature and while a viscosity of the first solution is equal to or higher than a set first viscosity;
mounting a semiconductor chip in the semiconductor chip mounting region, wherein the mounting of the semiconductor chip includes electrically connecting the semiconductor chip to the substrate pad; and
filling a region under the semiconductor chip and a region defined by the raised portion with an underfill by depositing the first solution while the temperature of the first solution is equal to or higher than the set first temperature and while the viscosity of the first solution is below the set first viscosity.

23. The method of claim 22 , further comprising simultaneously curing the raised portion and the underfill by applying a constant second temperature higher than the set first temperature.

24. The method of claim 22 , wherein the set first viscosity has a value in a range from about 1000 mPa·s to about 1500 mPa·s.

25. The method of claim 22 , wherein the set first temperature has a value in a range from bout 40° C. to about 50° C.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Han Seong-Chan
• Lee Young-rock
• Kang Chang-Kun
• Lee Chil-hoon
• Kim Han-Ju

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W72/387

  Flow barriers · CPC title