Anti-fuse type one-time programmable memory cell array and method of operating the same

Patent metadata

Field	Value
Publication number	US-9922721-B2
Application number	US-201615267859-A
Country	US
Kind code	B2
Filing date	Sep 16, 2016
Priority date	Nov 18, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An anti-fuse type one-time programmable (OTP) memory cell array includes a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a well region shared by the plurality of unit cells, a plurality of anti-fuse gates respectively disposed in the plurality of columns to intersect the well region, a plurality of source/drain regions respectively disposed in portions of the well region between the plurality of anti-fuse gates, and a plurality of drain regions respectively disposed in portions of the well region located at one sides of the anti-fuse gates arrayed in a last column, which are opposite to the anti-fuse gates arrayed in a first column. Each of the unit cells includes one anti-fuse transistor having a MOS transistor structure without a selection transistor.

First claim

What is claimed is:

1. A method of operating an anti-fuse type one-time programmable (OTP) memory cell array including a plurality of unit cells which are respectively located at cross points of a plurality of rows and a plurality of columns, a plurality of word lines respectively disposed in the plurality of columns, a plurality of well regions respectively disposed in the plurality of rows, wherein each of the well regions is shared by the unit cells in the same row, a plurality of well bias lines respectively connected to the plurality of well regions, a plurality of bit lines respectively connected to drain terminals of the unit cells arrayed in a last column of the plurality of columns, and a plurality of PN diodes coupled between the plurality of well bias lines and the drain terminals of the plurality of unit cells, the method comprising:
selecting one of the plurality of rows; and
sequentially programming the unit cells which are arrayed in the selected row,
wherein each of the plurality of unit cells includes an anti-fuse transistor having a metal-oxide-semiconductor (MOS) transistor structure without a selection transistor.

2. The method of claim 1 , wherein the selecting one of the plurality of rows comprises:
applying a ground voltage to one selected from the plurality of well bias lines; and
applying a second program voltage to the non-selected well bias lines arrayed in rows to be programmed in subsequent steps.

3. The method of claim 2 , wherein the sequentially programming the unit cells which are arrayed in the selected row comprises:
selectively applying a first program voltage to one of the plurality of word lines, which is connected to one selected from the unit cells;
applying the second program voltage to the non-selected word lines;
selectively applying a ground voltage to one of the plurality of bit lines, which is connected to the selected row; and
electrically floating or grounding the non-selected bit lines.

4. The method of claim 3 , wherein, when at least one of the unit cells has a programmed state before the selected unit cell is programmed, the word line connected to the at least one unit cell in the programmed state is electrically floated while the selected unit cell is programmed.

5. The method of claim 3 ,
wherein a voltage difference between the first program voltage applied to the selected word line and the ground voltage applied to the selected bit line has a voltage level to rupture an anti-fuse insulation layer of the anti-fuse transistor,
wherein the second program voltage is greater than a threshold voltage of the anti-fuse transistor; and
wherein a voltage difference between the second program voltage applied to the non-selected word lines and the ground voltage applied to the selected bit line has a voltage level which is insufficient to rupture an anti-fuse insulation layer of the anti-fuse transistor.

6. The method of claim 1 , further comprising:
performing a read operation for reading out data stored in the plurality of unit cells in units of rows,
wherein the data stored in the unit cells which are arrayed in any one selected from the plurality of rows are simultaneously read out during the read operation, and
wherein the performing the read operation comprises:
applying a ground voltage to all of the plurality of word lines;
electrically floating all of the plurality of bit lines;
applying a read voltage to one selected from the plurality of well bias lines; and
electrically floating the non-selected well bias lines.

7. The method of claim 6 , wherein the read voltage has a voltage level which is greater than a turn-on voltage of the PN diodes.

8. The method of claim 6 , wherein the read operation for reading out the data of the unit cells in the selected row is performed by detecting current that flows through each of the plurality of word lines.

9. The method of claim 1 , wherein the sequentially programming the unit cells which are arrayed in the selected row comprises:
sequentially programming from the unit cell of the first column in the selected row to the unit cell of the last column in the selected row.

Assignees

• Sk Hynix Inc

Inventors

• Song Hyun Min

Classifications

• H10W20/491

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H01L23/5252

  Electricity · mapped topic

• H01L27/11206

  Electricity · mapped topic

• G11C17/165

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• G11C17/16 Primary

  using electrically-fusible links · CPC title