Architecture for CMOS under array

Patent metadata

Field	Value
Publication number	US-9922716-B2
Application number	US-201715439858-A
Country	US
Kind code	B2
Filing date	Feb 22, 2017
Priority date	Apr 23, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Systems and methods for reducing the area and improving the performance of a non-volatile memory array are described. The non-volatile memory array may comprise a 3D NAND memory array that includes vertical NAND strings that are arranged orthogonal to a substrate. A vertical NAND string may include floating gate memory cell transistors or charge trap memory cell transistors. Sensing circuitry for sensing the programmed data states of memory cell transistors within the vertical NAND strings may be positioned underneath the 3D NAND memory array and connections from bit lines positioned above the 3D NAND memory array may be made using vertical connections extending though the 3D NAND memory array or through memory breaks within the 3D NAND memory array.

First claim

What is claimed is:

1. An apparatus, comprising:
a first sense amplifier arranged below a first portion of a memory array;
a second sense amplifier arranged below a second portion of the memory array;
a third sense amplifier arranged below a third portion of the memory array;
a first bit line arranged above the first portion of the memory array and the second portion of the memory array, the first bit line connects to the first sense amplifier via a first vertical connection positioned between the first portion of the memory array and the second portion of the memory array, the first bit line connects to a first set of memory cells within the first portion of the memory array and connects to a second set of memory cells within the second portion of the memory array, the first sense amplifier configured to sense one of the first set of memory cells during a sensing operation;
a second bit line arranged above the first portion and the second portion, the second bit line connects to the second sense amplifier via a second vertical connection positioned between the first portion of the memory array and the second portion of the memory array, the second bit line connects to a third set of memory cells within the first portion of the memory array and connects to a fourth set of memory cells within the second portion of the memory array, the second sense amplifier configured to sense one of the third set of memory cells during the sensing operation; and
a third bit line arranged above the second portion of the memory array and the third portion of the memory array, the third bit line connects to the third sense amplifier via a third vertical connection positioned between the second portion of the memory array and the third portion of the memory array, the third bit line connects to a fifth set of memory cells within the first portion of the memory array and connects to a sixth set of memory cells within the third portion of the memory array, the third sense amplifier configured to sense one of the fifth set of memory cells during the sensing operation.

2. The apparatus of claim 1 , wherein:
the sensing operation comprises a read operation.

3. The apparatus of claim 1 , wherein:
the sensing operation comprises a verify operation.

4. The apparatus of claim 1 , wherein:
the first bit line is arranged above the third portion of the memory array; and
the second bit line is arranged above the third portion of the memory array.

5. The apparatus of claim 1 , wherein:
the third bit line is arranged above the first portion of the memory array.

6. The apparatus of claim 1 , wherein:
the first portion of the memory array includes a plurality of 3D NAND strings.

7. The apparatus of claim 1 , wherein:
the first set of memory cells corresponds with a first vertical NAND string.

8. The apparatus of claim 1 , wherein:
the first set of memory cells corresponds with a set of floating gate transistors.

9. The apparatus of claim 1 , wherein:
the first set of memory cells corresponds with a set of charge trap transistors.

10. The apparatus of claim 1 , wherein:
the memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

11. A system, comprising:
a first sensing circuit positioned below a first portion of a memory array;
a third sensing circuit positioned below a third portion of the memory array; and
a second sensing circuit positioned below a second portion of the memory array, the first sensing circuit is connected to a first bit line positioned above the first portion of the memory array and the second portion of the memory array via a first vertical connection between the first portion of the memory array and the second portion of the memory array, the first bit line connects to a first set of memory cells within the first portion of the memory array and connects to a second set of memory cells within the second portion of the memory array, the first sensing circuit configured to sense one of the first set of memory cells during a sensing operation, the second sensing circuit is connected to a second bit line positioned above the first portion of the memory array and the second portion of the memory array via a second vertical connection between the first portion of the memory array and the second portion of the memory array, the second bit line connects to a third set of memory cells within the first portion of the memory array and connects to a fourth set of memory cells within the second portion of the memory array, the second sensing circuit configured to sense one of the third set of memory cells during the sensing operation, a third bit line arranged above the second portion of the memory array and the third portion of the memory array, the third bit line connects to the third sensing circuit via a third vertical connection positioned between the second portion of the memory array and the third portion of the memory array, the third bit line connects to a fifth set of memory cells within the first portion of the memory array and connects to a sixth set of memory cells within the third portion of the memory array, the third sensing circuit configured to sense one of the fifth set of memory cells during the sensing operation.

12. The system of claim 11 , wherein:
the sensing operation comprises a read operation.

13. The system of claim 12 , wherein:
the first bit line is arranged above the third portion of the memory array; and
the second bit line is arranged above the third portion of the memory array.

14. The system of claim 11 , wherein:
the first sensing circuit comprises a sense amplifier configured to determine a programmed data state of one of the second set of memory cells during a memory operation.

15. The system of claim 11 , wherein:
the second sensing circuit is connected to the second bit line via a bit line decoder.

16. The system of claim 11 , wherein:
the first portion of the memory array includes a first plurality of 3D NAND strings.

17. The system of claim 11 , wherein:
the first set of memory cells corresponds with a set of floating gate transistors.

18. The system of claim 11 , wherein:
the memory array is monolithically formed in one or more physical levels of memory cells having active areas disposed above a silicon substrate.

19. An apparatus, comprising:
a first sensing circuit arranged below a first portion of a three-dimensional NAND memory array, the first sensing circuit is connected to a first bit line driver, the first bit line driver electrically connects a first bit line arranged above the first portion of the three-dimensional NAND memory array and a second portion of the three-dimensional NAND memory array to the first sensing circuit;
a third sensing circuit arranged below a third portion of the three-dimensional NAND memory array, the third sensing circuit is connected to a third bit line driver, the third bit line driver electrically connects a third bit line arranged above the second portion of the three-dimensional NAND memory array and the third portion of the three-dimensional NAND memory array; and
a second sensing circuit arranged below the second portion of the three-dimensional NAND memory array, the second sensing circuit is connected to a second bit line driver, the second bit line driver electrically connects a second bit line arranged above the first portion of the three-dimensional NAND memory array and the second portion of the three-dimensional NAND memory array to the second

Assignees

• Sandisk Technologies Llc

Inventors

• Hsiung Chia-Lin
• An Yanbin
• Chu Alexander
• Toyama Fumiaki

Classifications

• G11C16/0466

  comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] (G11C16/0483, G11C16/0491 take precedence) · CPC title

• G11C16/3459

  Circuits or methods to verify correct programming of nonvolatile memory cells · CPC title

• G11C16/08

  Address circuits; Decoders; Word-line control circuits · CPC title

• G11C16/10

  Programming or data input circuits · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title