Resistive memory write circuitry with bit line drive strength based on storage cell line resistance

Patent metadata

Field	Value
Publication number	US-9922691-B2
Application number	US-201615062073-A
Country	US
Kind code	B2
Filing date	Mar 5, 2016
Priority date	Dec 24, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An apparatus is described that includes a bit line. The apparatus also includes first and second storage cells coupled to the bit line. The first storage cell has a first access transistor. The first access transistor is coupled to a first line resistance. The second storage cell has a second access transistor. The second access transistor is coupled to a second line resistance. The second line resistance is greater than the first line resistance. The apparatus also includes first and second drivers that are coupled to the bit line. The second driver is a stronger driver than the first driver. The apparatus also includes circuitry to select the first driver to write information into the first storage cell and select the second driver to write information into the second storage cell.

First claim

The invention claimed is:

1. A random access
memory, comprising: a bit line;
a first storage cell and a second storage cell coupled to the bit line;
driver circuitry to drive a first write current along a first current path comprising the bit line and the first storage cell, the driver circuitry to drive a second write current along a second current path comprising the bit line and the second storage cell, the first write current to write data into the first storage cell, the second write current to write data into the second storage cell, the first current path having greater resistance than the second current path, the first write current greater than the second write current.

2. The random access memory of claim 1 wherein the driver circuitry comprises a first driver to drive the first write current and a second driver to drive the second write current.

3. The random access memory of claim 1 wherein said first and second storage cells are resistive storage cells.

4. The random access memory of claim 3 wherein said resistive storage cells are magnetic spin transfer torque magnetic storage cells.

5. The random access memory of claim 1 further comprising a second bit line, said first and second storage cells coupled between said bit line and said second bit line.

6. The random access memory of claim 5 where said first current path travels along longer distances of said bit line and said second bit line than said second current path.

7. The random access memory of claim 1 wherein said first current path travels along a longer distance of said bit line than said second current path.

8. The random access memory of claim 1 wherein said driver circuitry is to drive said first write current through a third storage cell to write to said third storage cell, said third storage cell coupled to said bit line next to said first storage cell.

9. A computing system, comprising:
a plurality of processing cores;
a memory controller;
a random access memory, said random access memory comprising a), b) and c) below:
a) a bit line;
b) a first storage cell and a second storage cell coupled to the bit line;
c) driver circuitry to drive a first write current along a first current path comprising the bit line and the first storage cell, the driver circuitry to drive a second write current along a second current path comprising the bit line and the second storage cell, the first write current to write data into the first storage cell, the second write current to write data into the second storage cell, the first current path having greater resistance than the second current path, the first write current greater than the second write current.

10. The computing system of claim 9 wherein the driver circuitry comprises a first driver to drive the first write current and a second driver to drive the second write current.

11. The computing system of claim 9 wherein said first and second storage cells are resistive storage cells.

12. The computing system of claim 11 wherein said resistive storage cells are magnetic spin transfer torque magnetic storage cells.

13. The computing system of claim 9 further comprising a second bit line, said first and second storage cells coupled between said bit line and said second bit line.

14. The computing system of claim 13 where said first current path travels along longer distances of said bit line and said second bit line than said second current path.

15. The computing system of claim 9 wherein said first current path travels along a longer distance of said bit line than said second current path.

16. The computing system of claim 9 wherein said driver circuitry is to drive said first write current through a third storage cell to write to said third storage cell, said third storage cell coupled to said bit line next to said first storage cell.

Assignees

• Intel Corp

Inventors

• Jain Pulkit
• Hamzaoglu Fatih
• Wei Liqiong

Classifications

• G11C11/1675 Primary

  Writing or programming circuits or methods · CPC title

• G11C11/1655 Primary

  Bit-line or column circuits · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F3/0634

  by changing the state or mode of one or more devices · CPC title

• G11C11/1659

  Cell access · CPC title