Liquid crystal display device and driving method thereof

Patent metadata

Field	Value
Publication number	US-9922607-B2
Application number	US-15370808-A
Country	US
Kind code	B2
Filing date	May 22, 2008
Priority date	May 25, 2007
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A liquid crystal display (LCD) device includes a liquid crystal display panel having a matrix of liquid crystal cells defined by crossings of the data lines and the gate lines. The LCD device includes a data driving circuit for inverting a polarity of a data voltage in response to a polarity control signal, and supplying the polarity-inverted data voltage to an associated one of the data lines in response to a source output enable signal; a gate driving circuit for sequentially supplying a scan voltage to each of the gate lines in response to a gate output enable signal; and a controller for modulating the polarity control signal such that data voltages having the same polarity are respectively supplied to liquid crystal cells along one gate line in consecutive frame periods and generating the source output enable signal and the gate output enable signal.

First claim

What is claimed is:

1. A liquid crystal display device comprising:
a liquid crystal display panel having a plurality of data lines that cross a plurality of gate lines, defining a matrix of a plurality of liquid crystal cells;
a controller that outputs a polarity control signal, a source output enable signal, and a gate output enable signal;
a data driving circuit that supplies data voltages to the plurality of data lines in response to the source output enable signal; and
a gate driving circuit that sequentially supplies a scan voltage to each of the plurality of gate lines in response to the gate output enable signal;
wherein the polarity control signal is generated by the controller in accordance with an interlace driving scheme in which the data voltages are supplied to liquid crystal cells of the plurality of liquid crystal cells that are connected to odd-numbered gate lines of the plurality of gate lines during odd-numbered frame periods, while being supplied to liquid crystal cells of the plurality of liquid crystal cells that are connected to even-numbered gate lines of the plurality of gate lines during even-numbered frame periods, except when the controller determines that a counted frame number is equal to a counted number of one of the plurality of gate lines that is supplied with the scan voltage,
wherein when the controller determines that the counted frame number is equal to the counted number of one of the plurality of gate lines that is supplied with the scan voltage, a logic value of the polarity control signal is inverted, and
wherein when the controller determines that the counted frame number is equal to the counted number of one of the plurality of gate lines that is supplied with the scan voltage, the controller increases a pulse width of both the gate output enable signal and the source output enable signal.

2. The liquid crystal display device according to claim 1 , wherein the selected one of the gate lines is sequentially shifted by one gate line at intervals of one frame period.

3. The liquid crystal display device according to claim 1 , wherein the controller increases a pulse width of at least one of the gate output enable signal and the source output enable signal when a gate line of the plurality of gate lines having the same number as a frame number of a second one of the pair of consecutive frame periods is scanned to reduce a charge amount of data voltage supplied to liquid crystal cells along the gate line having the same number as a frame number of a second one of the pair of consecutive frame periods.

Assignees

• Song Hong Sung
• Min Woong Ki
• Jang Su Hyuk
• Lg Display Co Ltd

Inventors

• Song Hong Sung
• Min Woong Ki
• Jang Su Hyuk

Classifications

• G09G3/3614 Primary

  Control of polarity reversal in general · CPC title

• G09G2310/0224

  Details of interlacing · CPC title

• G09G2320/0247

  Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes · CPC title

• G09G3/3677

  suitable for active matrices only · CPC title

• G09G3/3648

  using an active matrix (G09G3/367 - G09G3/3696 take precedence) · CPC title