Device and method to assign device pin functionality for multi-processor core devices

Patent metadata

Field	Value
Publication number	US-9921988-B2
Application number	US-201514729402-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Jun 5, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device may have an output, a housing with a plurality of assignable external pins, and a plurality of peripheral pin selection modules for each processing core, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the processor cores.

First claim

The invention claimed is:

1. An embedded device comprising:
a plurality of microcontrollers, each comprising a central processing unit (CPU) and a plurality of peripheral devices, wherein each peripheral device may comprise an output;
a housing comprising a plurality of assignable external pins; and
a plurality of peripheral pin selection modules for each microcontroller, wherein each peripheral pin selection module is configured to be programmable to assign an assignable external pin to one of the plurality of peripheral devices of one of the microcontrollers.

2. The embedded device according to claim 1 , wherein each peripheral pin selection module is programmable only by the associated microcontrollers.

3. The embedded device according to claim 2 , wherein each peripheral pin selection module comprises a multiplexer providing an output signal for a single external pin and a plurality of inputs coupled with outputs of peripheral devices of a single microcontroller of the plurality of microcontrollers.

4. The embedded device according to claim 2 , wherein each microcontroller comprises memory that cannot be accessed by other microcontrollers.

5. The embedded device according to claim 4 , wherein the memory comprises flash memory and random access memory (RAM).

6. The embedded device according to claim 4 , wherein each peripheral pin selection module is controlled by a special function register.

7. The embedded device according to claim 6 , wherein the special function register is memory mapped into the RAM.

8. The embedded device according to claim 1 , wherein each microcontroller has a number of external pins assigned to it exclusively.

9. The embedded device according to claim 1 , further comprising ownership logic programmable to assign an external pin to any of the plurality of microcontrollers.

10. The embedded device according to claim 9 , wherein ownership of an external pin is programmed into configuration bits stored into flash memory.

11. A method for selecting output functionality of external pins in an embedded device comprising multiple microcontrollers, comprising:
arranging a plurality of microcontrollers on a single chip, wherein each microcontroller comprises a central processing unit and an associated plurality of peripheral devices, wherein each peripheral device may comprise an output;
arranging a plurality of peripheral pin selection modules for each microcontroller on said single chip, and
programming at least one of the peripheral pin selection modules by an associated central processing unit to couple an assignable external pin to one of the plurality of peripheral devices of the respective microcontroller.

12. The method according to claim 11 , wherein each peripheral pin selection module is programmable only by the associated central processing unit.

13. The method according to claim 12 , wherein each peripheral pin selection module comprises a multiplexer providing an output signal for a single external pin and a plurality of inputs coupled with outputs of peripheral devices of a single microcontroller of the plurality of microcontrollers.

14. The method according to claim 12 , wherein each microcontroller comprises memory that cannot be accessed by other microcontrollers.

15. The method according to claim 14 , wherein the memory comprises flash memory and random access memory (RAM).

16. The method according to claim 14 , further comprising the step of controlling each peripheral pin selection module by a special function register.

17. The method according to claim 16 , further comprising the step of memory mapping the special function register into the RAM.

18. The method according to claim 11 , wherein each microcontroller has a number of external pins assigned to it exclusively.

19. The method according to claim 11 , further comprising the step of providing ownership logic programmable to assign an external pin to any of the plurality of microcontrollers.

20. The method according to claim 19 , further comprising the step of programming ownership data of an external pin into configuration bits stored into flash memory.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan

Classifications

• G06F15/76 Primary

  Architectures of general purpose stored program computers (with program plugboard G06F15/08; multicomputers G06F15/16) · CPC title

• G06F1/22

  Means for limiting or controlling the pin/gate ratio · CPC title

• G06F13/385 Primary

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/287

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title