Device and method to assign device pin ownership for multi-processor core devices

Patent metadata

Field	Value
Publication number	US-9921982-B2
Application number	US-201514729879-A
Country	US
Kind code	B2
Filing date	Jun 3, 2015
Priority date	Jun 5, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

An embedded device has a plurality of processor cores, each with a plurality of peripheral devices, wherein each peripheral device has an output. Furthermore, a housing with a plurality of assignable external pins and a protected pin ownership logic for each assignable external pin is provided and configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores.

First claim

The invention claimed is:

1. An embedded device comprising:
a plurality of processor cores, each comprising a plurality of peripheral devices, wherein each peripheral device may comprise an output;
a housing comprising a plurality of assignable external pins; and
a protected pin ownership logic for each assignable external pin and configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores.

2. The embedded device according to claim 1 , wherein the protected pin ownership logic comprises a multiplexer having as many inputs as processor cores of the embedded device and a single output.

3. The embedded device according to claim 1 , wherein the protected pin ownership logic further comprises a locking logic configured to prevent a re-assignment of the associated assignable external pin.

4. The embedded device according to claim 1 , wherein the protected pin ownership logic comprises a configuration register configured to select a processing core through a multiplexer.

5. The embedded device according to claim 4 , wherein the configuration register is arranged in flash memory of the associated processing core.

6. The embedded device according to claim 5 , wherein a specified write sequence is necessary to write to the configuration register.

7. The embedded device according to claim 1 , wherein each processor comprises for each assignable external pin a peripheral pin select module that is configured to select an output of one of the plurality of peripheral devices associated with that processor.

8. The embedded device according to claim 7 , wherein each peripheral pin select module is configured to be controllable only by the associated processing core.

9. The embedded device according to claim 7 , wherein the peripheral pin select module comprises a special function register controlling a multiplexer.

10. The embedded device according to claim 1 , wherein each processing core is a 32 bit processing core and the housing comprises less than or equal to 32 external pins.

11. The embedded device according to claim 10 , wherein the housing comprises 28 external pins.

12. The embedded device according to claim 1 , wherein an input functionality of an external pin can be routed to more than one peripheral device or processing cores.

13. A method for arranging multiple processing cores in an embedded device comprising the steps of:
arranging a plurality of processor cores in a housing, each comprising a plurality of peripheral devices, wherein each peripheral device may comprise an output, and wherein the housing comprises a plurality of assignable external pins; and
providing for each assignable external pin a protected pin ownership logic configured to be programmable to assign an output function of an associated assignable external pin to only one of the plurality of processor cores.

14. The method according to claim 13 , the method comprising the step of controlling a multiplexer within the protected pin ownership logic, the multiplexer having as many inputs as processor cores of the embedded device and a single output.

15. The method according to claim 13 , the method further comprising the step of controlling a locking logic within the protected pin ownership logic to prevent a re-assignment of the associated assignable external pin.

16. The method according to claim 13 , the method further comprising the step of programming a configuration register to select a processing core through a multiplexer.

17. The method according to claim 16 , wherein at reset of the embedded device, a pin configuration stored in said configuration register is transferred to a multiplexer control for selecting an output.

18. The method according to claim 16 , wherein the configuration register is arranged in flash memory of the associated processing core.

19. The method according to claim 18 , wherein a specified write sequence is necessary to write to the configuration register.

20. The method according to claim 13 , wherein each processor comprises for each assignable external pin a peripheral pin select module and the method comprises select an output of one of the plurality of peripheral devices associated with that processor through a multiplexer of the peripheral pin select module.

21. The method according to claim 20 , wherein each peripheral pin select module is configured to be controllable only by the associated processing core.

22. The method according to claim 20 , wherein an input functionality of an external pin can be routed to more than one peripheral device or processing cores.

Assignees

• Microchip Tech Inc

Inventors

• Kris Bryan

Classifications

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/287 Primary

  Multiplexed DMA (G06F13/30 takes precedence) · CPC title

• G06F15/7814 Primary

  Specially adapted for real time processing, e.g. comprising hardware timers · CPC title

• H03K19/1732

  by limitation or reduction of the pin/gate ratio (for data-processing equipment G06F1/22) · CPC title