Method and apparatus for recovering abnormal data in internal memory

US9921925B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9921925-B2
Application numberUS-201414579577-A
CountryUS
Kind codeB2
Filing dateDec 22, 2014
Priority dateApr 22, 2013
Publication dateMar 20, 2018
Grant dateMar 20, 2018

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently being executed by the processor; if it is determined that the abnormal instruction belongs to the program unit and that instructions between the first instruction and the current instruction in the program unit are all reversible instructions, invoking a destruction program unit corresponding to the program unit, so as to release resources already applied for by the program unit; and causing the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit.

First claim

Opening claim text (preview).

What is claimed is: 1. A method for recovering abnormal data in an internal random access memory (RAM), the method comprising: reading data stored in a first portion of the internal RAM, the first portion storing at least one instruction; checking the read data and, when it is determined that the read data is abnormal, generating an abnormality signal; receiving, by a processor, the abnormality signal and an address of the at least one instruction; suspending, by the processor, a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining, by the processor according to the address pointed to by the computer pointer, an address segment of a program unit currently being executed by the processor; determining, by the processor, whether the address of the at least one instruction belongs to the program unit; when the address of the at least one instruction belongs to the program unit, determining, by the processor, whether instructions between a first instruction and the current instruction in the program unit are all reversible instructions; when the instructions are all reversible instructions, invoking, by the processor, a destruction program unit corresponding to the program unit; causing, by the processor, the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit, to recover the abnormal data in the internal memory; wherein: determining, by the processor, whether instructions between a first instruction and the current instruction in the program unit are all reversible instructions comprises: determining, by the processor, whether the program unit is reversible, wherein reversibility of the program unit means that no instruction in the program unit comprises a destructive operation, and when the program unit is irreversible, obtaining, by the processor, an address of a first irreversible instruction in the program unit, and determining whether the address of the first irreversible instruction is after the address pointed to by the computer pointer; and invoking, by the processor, the destruction program unit corresponding to the program unit comprises: when the program unit is reversible or the address of the first irreversible instruction is after the address pointed to by the computer pointer, invoking, by the processor, the destruction program unit corresponding to the program unit, to release resources already applied for by the program unit. 2. The method according to claim 1 , wherein: determining, by the processor, whether the program unit is reversible comprises: obtaining, by the processor, a reversible matrix of the program unit, and querying whether the program unit is reversible in the reversible matrix of the program unit, wherein the reversible matrix comprises reversibility information of the program unit; and obtaining, by the processor, an address of a first irreversible instruction in the program unit comprises: obtaining, by the processor, a start address of the program unit, and obtaining an offset of the first irreversible instruction from the reversible matrix, and using, by the processor, a sum of the start address and the offset as the address of the first irreversible instruction. 3. A method for recovering abnormal data in an internal random access memory (RAM), the method comprising: reading data stored in a first portion of the internal RAM, the first portion storing at least one instruction; checking the read data and, when it is determined that the read data is abnormal, generating an abnormality signal; receiving, by a processor, the abnormality signal and an address of the at least one instruction; suspending, by the processor, a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining, by the processor according to the address pointed to by the computer pointer, an address segment of a program unit currently being executed by the processor; determining, by the processor, whether the address of the at least one instruction belongs to the program unit; when the address of the at least one instruction belongs to the program unit, determining, by the processor, whether instructions between a first instruction and the current instruction in the program unit are all reversible instructions; when the instructions are all reversible instructions, invoking, by the processor, a destruction program unit corresponding to the program unit; causing, by the processor, the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit, to recover the abnormal data in the internal memory; wherein: the internal memory comprises a buffer memory; and after invoking, by the processor, a destruction program unit corresponding to the program unit, and, before causing, by the processor, the computer pointer to point back to an address of the first instruction in the program unit, the method further comprises: obtaining, by the processor from a cache-storage mapping table, a cache address of data in the instructions between the first instruction and the current instruction in the program unit, and setting a cache space pointed to by the cache address in the buffer memory to be invalid. 4. The method according to claim 3 , wherein: the buffer memory comprises a level-1 buffer memory and a level-2 buffer memory. 5. A method for recovering abnormal data in an internal random access memory (RAM), the method comprising: reading data stored in a first portion of the internal RAM, the first portion storing at least one instruction; checking the read data and, when it is determined that the read data is abnormal, generating an abnormality signal; receiving, by a processor, the abnormality signal and an address of the at least one instruction; suspending, by the processor, a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining, by the processor according to the address pointed to by the computer pointer, an address segment of a program unit currently being executed by the processor; determining, by the processor, whether the address of the at least one instruction belongs to the program unit; when the address of the at least one instruction belongs to the program unit, determining, by the processor, whether instructions between a first instruction and the current instruction in the program unit are all reversible instructions; when the instructions are all reversible instructions, invoking, by the processor, a destruction program unit corresponding to the program unit; causing, by the processor, the computer pointer to point back to an address of the first instruction in the program unit, and re-executing the program unit, to recover the abnormal data in the internal memory; and wherein when an irreversible instruction exists between the first instruction and the current instruction in the program unit, or the address of the at least one instruction does not belong to the program unit, performing, by the processor, a system resetting operation, to recover the abnormal data in the internal memory. 6. An apparatus for recovering abnormal data in an internal random access memory (RAM), the apparatus comprising: a processor; memory coupled to the processor, the memory comprising instructions that, when executed by the processor, cause the apparatus to: receive an abnormality signal and an address of an abnormal instruction where abnormal data is located, the abnormality signal generated in response to reading data stored in a first portion of the internal RAM, checking the read data, and determining that the read data is abnormal, suspend a current instruction being e

Assignees

Inventors

Classifications

  • Dumping, i.e. gathering error/state information after a fault for later diagnosis · CPC title

  • Restarting or rejuvenating · CPC title

  • where memory access, memory control or I/O control functionality is redundant (redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089) · CPC title

  • Instruction analysis, e.g. decoding, instruction word fields · CPC title

  • Error detection or correction of the data by redundancy in operations (error detection or correction of the data by redundancy in hardware G06F11/16) · CPC title

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What does patent US9921925B2 cover?
The present invention discloses a method and an apparatus for recovering abnormal data in an internal memory. The method includes: receiving, by a processor, a data abort signal and an address of an abnormal instruction where abnormal data is located; suspending a current instruction being executed, and recording an address pointed to by a computer pointer; obtaining a program unit currently be…
Who is the assignee on this patent?
Huawei Tech Co Ltd
What technology area does this patent fall under?
Primary CPC classification G06F11/2017. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Mar 20 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).