Management of power loss in a memory device

Patent metadata

Field	Value
Publication number	US-9921916-B2
Application number	US-201514975272-A
Country	US
Kind code	B2
Filing date	Dec 18, 2015
Priority date	Dec 18, 2015
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Provided is a memory device, comprising a non-volatile memory, an energy store coupled to an input power module of the non-volatile memory, and a power management module configurable to determine whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line. Provided also is a computational device that includes the memory device. Provided also is a method in which a power management module of the memory device determines whether or not to supply backup power to the non-volatile memory via the energy store to initiate a shutdown process, based on differentiating a voltage glitch from an actual loss of power in a power line.

First claim

What is claimed is:

1. A memory device, comprising:
a non-volatile memory;
an energy store coupled to an input power module of the non-volatile memory;
a switch coupled to a power line to control transmission of power to the non-volatile memory; and
a power management module configurable to:
determine whether a voltage drop has occurred, wherein the voltage drop occurs either via a voltage glitch or via an actual loss of power;
turn off the switch, in response to determining that the voltage drop has occurred;
determine that the actual loss of power has occurred, in response to turning off the switch; and
control the energy store to supply power to the non-volatile memory, in response to determining that the actual loss of power has occurred.

2. The memory device of claim 1 , wherein the power management module is further configurable to:
maintain the switch in a state in which the power line is able to supply power to the non-volatile memory, in response to determining that no voltage drop has occurred; and
preserve energy in a source power rail of the switch for a time interval between the determining of the voltage drop and the determining of the actual loss of power.

3. The memory device of claim 1 , wherein the power management module is further configurable to:
maintain or restore the switch in a state in which the power line is able to supply power to the non-volatile memory, in response to determining that no actual loss of power has occurred.

4. The memory device of claim 1 , wherein the memory device is a memory board or a storage drive, wherein the non-volatile memory comprises a plurality of non-volatile memory chips, and wherein the energy store is a capacitor that is configurable to store charge.

5. The memory device of claim 1 , wherein the switch comprises two MOSFETs with a single gate that is controlled by the power management module, wherein
in response to a reverse voltage condition caused by a voltage drop detected by the switch, the power management module is configurable to disable the two MOSFETs via the single gate to preserve energy in a source power rail that couples the switch to the non-volatile memory.

6. The memory device of claim 1 , wherein:
the switch comprises a first MOSFET controlled by a first gate, and a second MOSFET controlled by a second gate; and
in response to a reverse voltage condition caused by a voltage drop detected by the switch, the power management module is configurable to disable the second MOSFET via the second gate.

7. A method, comprising:
maintaining a memory device comprising a non-volatile memory and an energy store;
controlling, via a switch coupled to a power line, transmission of power to the non-volatile memory; and
peforming operations by a power management module of the memory device, the operations comprising:
determining whether a voltage drop has occurred, wherein the voltage drop occurs either via a voltage glitch or via an actual loss of power;
turning off the switch, in response to determining that the voltage drop has occurred;
determining that the actual loss of power has occurred, in response to turning off the switch; and
controlling the energy store to supply power to the non-volatile memory, in response to determining that the actual loss of power has occurred.

8. The method of claim 7 , wherein the power management module further performs operations comprising:
maintaining the switch in a state in which the power line is able to supply power to the non-volatile memory, in response to determining that no voltage drop has occurred; and
preserving energy in a source power rail of the switch for a time interval between the determining of the voltage drop and the determining of the actual loss of power.

9. The method of claim 7 , wherein the power management module further performs operations comprising:
maintaining or restoring the switch in a state in which the power line is able to supply power to the non-volatile memory, in response to determining that no actual loss of power has occurred.

10. The method of claim 7 , wherein the memory device is a memory board or a storage drive, wherein the non-volatile memory comprises a plurality of non-volatile memory chips, and wherein the energy store is a capacitor that is configurable to store charge.

11. The method of claim 7 , wherein the switch comprises two MOSFETs that share a single gate that is controlled by the power management module, and wherein in response to a reverse voltage condition caused by a voltage drop detected by the switch, the power management module disables the two MOSFETs via the single gate to preserve energy in a source power rail that couples the switch to the non-volatile memory.

12. The method of claim 7 , wherein:
the switch comprises a first MOSFET controlled by a first gate, and a second MOSFET controlled by a second gate; and
in response to a reverse voltage condition caused by a voltage drop detected by the switch, the power management module disables the second MOSFET via the second gate, wherein the first MOSFET continues to facilitate charge retention in a source power rail even when the second MOSFET is disabled.

13. A computational device, comprising:
a processor; and
a memory device coupled to the processor, the memory device comprising:
a non-volatile memory;
an energy store coupled to an input power module of the non-volatile memory;
a switch coupled to a power line to control transmission of power to the non-volatile memory; and
a power management module configurable to:
determine whether a voltage drop has occurred, wherein the voltage drop occurs either via a voltage glitch or via an actual loss of power;
turn off the switch, in response to determining that the voltage drop has occurred;
determine that the actual loss of power has occurred, in response to turning off the switch; and
control the energy store to supply power to the non-volatile memory, in response to determining that the actual loss of power has occurred.

14. The computational device of claim 13 , wherein the power management module is further configurable to:
maintain the switch in a state in which the power line is able to supply power to the non-volatile memory, in response to determining that no voltage drop has occurred; and
preserve energy in a source power rail of the switch for a time interval between the determining of the voltage drop and the determining of the actual loss of power.

15. The computational device of claim 13 , wherein the power management module is further configurable to:
maintain or restore the switch in a state in which the power line is able to supply power to the non-volatile memory, in response to determining that no actual loss of power has occurred.

16. The computational device of claim 13 , wherein the memory device is a memory board or a storage drive, wherein the non-volatile memory comprises a plurality of non-volatile memory chips, and wherein the energy store is a capacitor that is configurable to store charge.

17. The computational device of claim 13 , wherein the switch comprises two MOSFETs with a single gate that is controlled by the power management module, wherein
in response to a reverse voltage condition caused by a voltage drop detected by the switch, the power management module is configurable to disable the two MOSFETs via the single gate to preserve energy in a source power rail that couples the switch to the non-volatile memory.

18. The computational device of claim 13 , wherein:
the switch comprises a first MO

Assignees

• Intel Corp

Inventors

• Morning-Smith Andrew
• Mocanu Adrian
• Zupanc Zeljko
• Ngo Mike M

Classifications

• G06F1/305

  in the event of power-supply fluctuations · CPC title

• G06F13/4022

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• G06F11/1441 Primary

  Resetting or repowering · CPC title

• G06F1/263

  Arrangements for using multiple switchable power supplies, e.g. battery and AC (G06F1/30 takes precedence) · CPC title

• G06F9/442 Primary

  Shutdown · CPC title