Address expansion and contraction in a multithreading computer system

Patent metadata

Field	Value
Publication number	US-9921849-B2
Application number	US-201514828768-A
Country	US
Kind code	B2
Filing date	Aug 18, 2015
Priority date	Mar 27, 2014
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Embodiments relate to address expansion and contraction in a multithreading computer system. According to one aspect, a computer implemented method for address adjustment in a configuration is provided. The configuration includes a core configurable between an ST mode and an MT mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The primary thread is accessed in the ST mode using a core address value. Switching from the ST mode to the MT mode is performed. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value. The expanded address value includes the core address value concatenated with a thread address value.

First claim

What is claimed is:

1. A computer implemented method for address adjustment in a configuration comprising a core configurable between a single thread (ST) mode and a multithreading (MT) mode, the ST mode addressing a primary thread and the MT mode addressing the primary thread and one or more secondary threads on shared resources of the core, the method comprising:
accessing the primary thread in the ST mode using a core address value;
switching from the ST mode to the MT mode;
forming an expanded address value as a shifted core address value by shifting the core address value by an amount based on a requested maximum thread identifier and concatenating the shifted core address value with a thread address value;
accessing the primary thread or one of the one or more secondary threads in the MT mode using the expanded address value;
switching between the MT mode and the ST mode;
selecting the core address value to access the primary thread based on the core being in the ST mode; and
selecting the expanded address value to access the primary thread or one of the one or more secondary threads based on the core being in the MT mode.

2. The method according to claim 1 , wherein a standard-format address is used in the ST mode, and the core reverts from the MT mode to the ST mode based on disabling the MT mode.

3. The method according to claim 2 , wherein only the primary thread and not the one or more secondary threads is accessible based on disabling the MT mode.

Assignees

• IBM

Inventors

• Bradbury Jonathan D
• Busaba Fadi Y
• Farrell Mark S
• Gainey Jr Charles W
• Greiner Dan F
• Heller Lisa Cranton
• Kubala Jeffrey P
• Osisek Damian L
• Schmidt Donald W
• Slegel Timothy J

Classifications

• G06F9/30189

  according to execution mode, e.g. mode flag · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/5077 Primary

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title

• G06F9/30145

  Instruction analysis, e.g. decoding, instruction word fields · CPC title

• G06F9/3851 Primary

  from multiple instruction streams, e.g. multistreaming · CPC title