Coordinated thread criticality-aware memory scheduling

Patent metadata

Field	Value
Publication number	US-9921839-B1
Application number	US-201615275066-A
Country	US
Kind code	B1
Filing date	Sep 23, 2016
Priority date	Sep 23, 2016
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

A multi-core processor includes a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics including stall cycle values, prefetches of a first type, and prefetches of a second type. The multi-core processor further includes criticality-aware thread prioritization (CATP) logic to compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values, identify a thread with a highest stall fraction of the plurality of threads, determine the highest stall fraction is greater than a stall threshold, prioritize demand requests of the identified thread, compute a prefetch accuracy of the identified thread during the interval using the prefetches of the first type and the prefetches of the second type, determine the prefetch accuracy is greater than a prefetch threshold, and prioritize prefetch requests of the identified thread.

First claim

What is claimed is:

1. A multi-core processor comprising:
a plurality of cores to execute a plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics comprising stall cycle values, a first number of prefetches of a first type, and a second number of prefetches of a second type; and
criticality-aware thread prioritization (CATP) logic to:
compute a stall fraction for each of the plurality of threads during the interval using the stall cycle values;
identify a thread from the plurality of threads with a highest stall fraction of the plurality of threads;
determine the highest stall fraction is greater than a stall threshold;
prioritize demand requests of the identified thread;
compute a prefetch accuracy of the identified thread during the interval using the first number of prefetches of the first type and the second number of prefetches of the second type;
determine the prefetch accuracy is greater than a prefetch threshold; and
prioritize prefetch requests of the identified thread.

2. The multi-core processor of claim 1 , wherein the CATP logic comprises:
first logic block to compute the stall fraction;
second logic block to compute the prefetch accuracy;
third logic block to prioritize the demand requests of the identified thread; and
fourth logic block to prioritize the prefetch requests of the identified thread.

3. The multi-core processor of claim 2 , wherein the first logic block and the second logic block reside in each of the plurality of cores.

4. The multi-core processor of claim 2 further comprising a memory controller, wherein the first logic block and the second logic block reside in each of the plurality of cores, wherein the third logic block and the fourth logic block reside in the memory controller.

5. The multi-core processor of claim 2 further comprising a memory controller, wherein the first logic block, the second logic block, the third logic block, and the fourth logic block reside in the memory controller.

6. The multi-core processor of claim 1 , wherein:
the prefetch accuracy is a ratio of the first number of prefetches of the first type to a sum of the first number of prefetches of the first type and the second number of prefetches of the second type;
prefetches of the first type is when corresponding data was brought into an L2 cache from main memory and the corresponding data was used by a subsequent demand request; and
prefetches of the second type is when corresponding data was brought into the L2 cache from the main memory and the corresponding data was evicted without being used.

7. The multi-core processor of claim 1 , wherein the stall fraction of a corresponding thread is a ratio of the stall cycles of the corresponding thread to a plurality of stall cycles of the plurality of threads.

8. The multi-core processor of claim 1 , wherein the CATP logic to prioritize the demand requests of the identified thread comprises processing the demand requests of the identified thread prior to processing a plurality of demand requests from the plurality of threads, wherein the CATP logic to prioritize the prefetch requests of the identified thread comprises processing the prefetch requests of the identified thread after processing the demand requests of the identified thread and prior to processing a plurality of prefetch requests from the plurality of threads.

9. A method comprising:
executing, by a plurality of cores, a plurality of threads;
monitoring, by the plurality of cores, metrics for each of the plurality of threads during an interval, the metrics comprising stall cycle values, a first number of prefetches of a first type, and a second number of prefetches of a second type; and
computing, by a first logic block of criticality-aware thread prioritization (CATP) logic, a stall fraction for each of the plurality of threads during the interval using the stall cycle values;
identifying, by the CATP logic, a thread from the plurality of threads with a highest stall fraction of the plurality of threads;
determining, by the CATP logic, the highest stall fraction is greater than a stall threshold;
prioritizing, by a third logic block of the CATP logic, demand requests of the identified thread;
computing, by a second logic block of the CATP logic, a prefetch accuracy of the identified thread during the interval using the first number of prefetches of the first type and the second number of prefetches of the second type;
determining, by the CATP logic, the prefetch accuracy is greater than a prefetch threshold; and
prioritizing, by a fourth logic block of the CATP logic, prefetch requests of the identified thread.

10. The method of claim 9 , wherein the first logic block and the second logic block reside in each of the plurality of cores.

11. The method of claim 9 , wherein the first logic block and the second logic block reside in each of the plurality of cores, wherein the third logic block and the fourth logic block reside in a memory controller.

12. The method of claim 9 , wherein the first logic block, the second logic block, the third logic block, and the fourth logic block reside in a memory controller.

13. The method of claim 9 , wherein:
the prefetch accuracy is a ratio of the first number of prefetches of the first type to a sum of the first number of prefetches of the first type and the second number of prefetches of the second type;
prefetches of the first type is when corresponding data was brought into an L2 cache from main memory and the corresponding data was used by a subsequent demand request; and
prefetches of the second type is when corresponding data was brought into the L2 cache from the main memory and the corresponding data was evicted without being used.

14. The method of claim 9 , wherein the stall fraction of a corresponding thread is a ratio of the stall cycles of the corresponding thread to a plurality of stall cycles of the plurality of threads.

15. The method of claim 9 , wherein:
the prioritizing of the demand requests of the identified thread comprises processing the demand requests of the identified thread prior to processing a plurality of demand requests from the plurality of threads; and
the prioritizing of the prefetch requests of the identified thread comprises processing the prefetch requests of the identified thread after processing the demand requests of the identified thread and prior to processing a plurality of prefetch requests from the plurality of threads.

16. A system comprising:
a main memory to receive a plurality of demand requests and a plurality of prefetch requests from a plurality of threads; and
a multi-core processor coupled to the main memory, the multi-core processor comprising:
a plurality of cores to execute the plurality of threads and to monitor metrics for each of the plurality of threads during an interval, the metrics comprising stall cycle values, a first number of prefetches of a first type, and a second number of prefetches of a second type; and
criticality-aware thread prioritization (CATP) logic to:
compute, by a first logic block of the CATP logic, a stall fraction for each of the plurality of threads during the interval using the stall cycle values;
identify a thread from the plurality of threads with a highest stall fraction of the plurality of threads;
determine the highest stall fraction is greater than a stall threshold;
prioritize, by a third logic block of the CATP logic, demand requests of the identified thread;
compute, by a second logic block of the CATP logic, a prefetch accuracy of the iden

Assignees

• Subramanian Lavanya
• Subramoney Sreenivas
• Bashyam Nithiyanandan
• Nori Anant
• Intel Corp

Inventors

• Subramanian Lavanya
• Subramoney Sreenivas
• Bashyam Nithiyanandan
• Nori Anant

Classifications

• G06F12/0862 Primary

  with prefetch · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F2212/602

  Details relating to cache prefetching · CPC title

• G06F9/3009 Primary

  Thread control instructions · CPC title

• G06F9/30047

  Prefetch instructions; cache control instructions · CPC title