Low dropout regulator with thin pass device

Patent metadata

Field	Value
Publication number	US-9921594-B1
Application number	US-201715487299-A
Country	US
Kind code	B1
Filing date	Apr 13, 2017
Priority date	Apr 13, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Systems, methods and apparatus for efficient control and biasing of pass devices that include at least one thin pass device and a remaining of thick pass devices. When operated at extreme high and low voltages, the at least one thin pass device maintains operation in its saturation region of operation while the remaining pass devices may be driven into their triode regions of operation. The thin and thick pass devices are arranged in a cascode configuration that includes a plurality of stacked devices. Biasing of the thin and thick cascode devices can be according to a voltage division scheme which protects the devices when the voltage across the stack is high, and provides a skewed voltage division across the stacked devices that promotes a higher gate-to-source voltage of the thick pass devices for a lower R ON . In one exemplary case, gate length of the at least one thin pass device may be reduced to provide a lower gate-to-source voltage of the thin pass device during operation in the saturation region. An exemplary implementation of an LDO controlling the pass devices for providing RF power to a power amplifier is described.

First claim

The invention claimed is:

1. A circuit arrangement comprising:
a stack of at least two transistors arranged in a cascode configuration, comprising an input transistor and a first cascode transistor; and
a biasing circuit configured to provide a first bias voltage to the first cascode transistor,
wherein:
a supply voltage to the stack is a varying supply voltage,
the first bias voltage is a function of the varying supply voltage and an output voltage at an output of the stack,
the varying supply voltage varies between a low supply voltage and a high supply voltage,
the output voltage is bound by a low output voltage and a high output voltage, and
a voltage gain of the biasing circuit is configured to change according to at least two conditions:
i) a first condition wherein the varying supply voltage is at the high supply voltage and the output voltage is at the low output voltage, and
ii) a second condition wherein the varying supply voltage is at the low supply voltage and the output voltage is at the high output voltage,
wherein the voltage gain of the biasing circuit during operation according to the first condition is higher than the voltage gain of the biasing circuit during operation according to the second condition, the voltage gain being defined as a ratio of the first bias voltage and the varying supply voltage.

2. The circuit arrangement according to claim 1 , wherein:
the input transistor has a shorter gate length than the first cascode transistor, and/or
the input transistor has a thin gate oxide layer and the first cascode transistor has a thick gate oxide layer.

3. The circuit arrangement according to claim 2 , wherein a thickness of the gate oxide layer of the input transistor is 30 Angstroms or less, and a thickness of the gate oxide layer of the first cascode transistor is 70 Angstroms or more.

4. The circuit arrangement according to claim 2 , wherein a ratio between a thickness of the gate oxide layer of the input transistor and a thickness of the gate oxide layer of the first cascode transistor is 0.5 or less.

5. The circuit arrangement according to claim 2 , wherein a gate length of the input transistor is 0.13 μm or shorter, and a gate length of the first cascode transistor is 0.30 μm or longer.

6. The circuit arrangement according to claim 2 , wherein a ratio of a gate length of the input transistor and a gate length of the first cascode transistor is 0.5 or less.

7. The circuit arrangement according to claim 1 , wherein the voltage gain continuously varies between a higher voltage gain during operation according to the first condition and a lower voltage gain during operation according to the second condition.

8. The circuit arrangement according to claim 1 , wherein the voltage gain discretely varies between a higher voltage gain during operation according to the first condition and a lower voltage gain during operation according to the second condition.

9. The circuit arrangement according to claim 1 , wherein the voltage gain varies between a higher voltage gain during operation according to the first condition and a lower voltage gain during operation according to the second condition in one or more of: a) continuously in segments, and b) in discrete steps.

10. The circuit arrangement according to claim 1 , wherein:
a voltage difference between the output voltage and the varying supply voltage define a voltage across the stack;
during operation according to the first condition, the first bias voltage is adapted to provide an unequal voltage division of the voltage across the stack over each of the at least two transistors, and
during operation according to the second condition, the first bias voltage is adapted to skew the unequal voltage division with a larger share of the voltage across the stack over the first cascode transistor.

11. The circuit arrangement according to claim 10 , wherein the first bias voltage is adapted to maintain operation of the input transistor in a saturation region during operation according to the first condition and the second condition.

12. The circuit arrangement according to claim 10 , wherein the first bias voltage is adapted to provide a larger gate to source voltage to the first cascode transistor during operation according to the second condition.

13. The circuit arrangement according to claim 12 , wherein during operation according to the second condition:
the first cascode transistor operates in a triode region, and
the larger gate to source voltage is adapted to provide a lower drain-to-source resistance of the first cascode transistor.

14. The circuit arrangement according to claim 1 , wherein the biasing circuit comprises:
a configurable resistive divider coupled between the varying supply voltage and a reference potential, wherein a first node of the configurable resistive divider carries the first biasing voltage.

15. The circuit arrangement according to claim 14 , wherein the biasing circuit further comprises:
a resistor comprising a first terminal coupled to the first node and a second terminal;
a transistor adapted to couple the second terminal of the resistor to the reference potential based on operation according to one of the first condition and second condition.

16. The circuit arrangement according to claim 15 , wherein the transistor is configured to operate as a voltage controlled variable resistor.

17. The circuit arrangement according to claim 15 , wherein the transistor is configured to operate as a switch.

18. The circuit arrangement according to claim 1 , wherein:
the stack is a pass device of a low dropout regulator (LDO) that provides a conduction path between a source of the input transistor of the stack connected to the varying supply voltage, and a drain of a last cascode transistor of the at least two transistors of the stack carrying the output voltage, said drain connected to a load,
responsive to a control voltage provided to the input transistor, the output voltage varies, and responsive to the control voltage and the varying supply voltage the biasing circuit operates according to the at least two conditions, wherein:
during operation according to the first condition, the at least two transistors of the stack operate in their respective saturation regions of operation,
during operation according to the second condition, the input transistor maintains operation in its respective saturation region of operation, and
during operation according to the second condition, the first cascode transistor operates in a respective triode region of operation, and the biasing circuit is adapted to reduce the first bias voltage to increase a gate-to-source voltage of the first cascode transistor for a reduction in a corresponding drain-to-source resistance.

19. A method for adjusting a bias voltage of a cascode transistor, the method comprising:
providing a stack of at least two transistors arranged in a cascode configuration, comprising an input transistor and the cascode transistor;
biasing, by a biasing circuit, the cascode transistor based on a varying supply voltage to the stack and an output voltage of the stack; and
based on the biasing, providing an unequal division of the varying supply voltage across the stack,
wherein:
the varying supply voltage varies between a low supply voltage and a high supply voltage,
the output voltage is bound by a low output voltage and a high output voltage, and
a voltage gain of the biasing circuit is configured to change according to at least two conditions:
i) a first cond

Assignees

• Peregrine Semiconductor Corp
• Psemi Corp

Inventors

• Kovac David
• Golat Joseph

Classifications

• G05F1/462

  as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic · CPC title

• G05F3/242

  with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage · CPC title

• G05F1/565 Primary

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G05F1/575

  characterised by the feedback circuit · CPC title

• G05F1/595

  semiconductor devices connected in series · CPC title