Production-level modularized load board produced using a general universal device interface for automatic test equipment for semiconductor testing

Patent metadata

Field	Value
Publication number	US-9921244-B1
Application number	US-201715414507-A
Country	US
Kind code	B1
Filing date	Jan 24, 2017
Priority date	Jan 24, 2017
Publication date	Mar 20, 2018
Grant date	Mar 20, 2018

Abstract

Embodiments of the present utilize a specialized modular load board in combination with previously-tested daughter boards to yield a final design for generating a new printed circuit board (PCB) for testing. Since the electrical characteristics of the daughter board are already known by the client and well established during previous testing procedures, similar test programs can be used for production-level testing that were used in client prototyping processes that involved the use of the previously-tested daughter board. Thus, embodiments of the present disclosure can use the features of the specialized modular load board and a client's tested daughter board to develop more reliable, production-ready circuits.

First claim

What is claimed is:

1. A method for testing a device under test (DUT), said method comprising:
characterizing electrical characteristics associated with a miniature load board, said miniature load board comprising a plurality of ports configured to electrically interface with a plurality of pin-socket connections adapted to receive a DUT;
using a prototype load board to design a connection layout between said miniature load board and a test head of a circuit tester, said prototype load board comprising:
said miniature load board removeably integrated therein;
a frame with mounting positions; and
a plurality of removable repositionable connectors for attachment to said frame and a plurality of flexible connections between said plurality of removable repositionable connectors and said plurality of ports, said prototype load board configured to electrically couple said miniature load board to electrical connections formed on a test head surface; and

fabricating a PCB based load board based on said connection layout, said PCB load board comprising a miniature load board mounting connector for loading said miniature load board during an operational testing mode thereof and permanent located connectors for connecting to said test head.

2. The method described in claim 1 , wherein said characterizing electrical characteristics further comprises characterizing electrical characteristics between said plurality of ports associated with said miniature load board and said plurality of pin-socket connections.

3. The method described in claim 2 , wherein said characterizing is performed at a client test environment.

4. The method described in claim 3 , wherein said client test environment further comprises using benchmark tests configured to measure signal characteristics between said plurality of ports and said plurality of pin-socket connections.

5. The method described in claim 1 , wherein fabricating a PCB based load board further comprises generating traces that route between final positions of said permanent located connectors to a final position of said miniature load board based on said connection layout.

6. The method described in claim 1 , wherein said plurality of ports comprises edge connectors.

7. The method described in claim 1 , wherein said miniature load board is a daughter board.

8. A load board assembly for testing a device under test (DUT), said assembly comprising:
a first portion, wherein said first portion comprises a miniature PCB based load board, said miniature PCB based load board comprising a plurality of ports configured to electrically interface with a plurality of pin-socket connections adapted to receive a DUT; and
a second portion, wherein said second portion comprises a PCB based load board comprising a miniature load board mounting location with connectors for loading said miniature PCB based load board during an operational mode thereof and a plurality of traces that route final positions of a plurality of permanent connectors to said connectors for loading said miniature PCB based load board, wherein said plurality of traces are determined using a prototype load board to a final position of said DUT.

9. The load board assembly described in claim 8 , wherein said first portion is electrically characterized within a client test environment.

10. The load board assembly described in claim 8 , wherein said prototype load board comprises:
said miniature PCB based load board removeably integrated therein;
a frame with mounting positions; and
a plurality of removable repositionable connectors for attachment to said frame and a plurality of flexible connections between said plurality of removable repositionable connectors and said plurality of ports, said prototype load board configured to electrically couple said miniature PCB based load board to electrical connections formed on a test head surface.

11. The load board assembly described in claim 9 , wherein said plurality of permanent connectors are positioned to mate with a test head of a circuit tester.

12. The load board assembly described in claim 9 , wherein said client test environment further comprises benchmark tests configured to measure signal characteristics between said plurality of ports and said plurality of pin-socket connections.

13. The method described in claim 8 , wherein said plurality of ports comprises edge connectors.

14. The load board assembly described in claim 8 , wherein said miniature PCB based load board is a daughter board.

15. A method for testing a device under test (DUT), said method comprising:
characterizing electrical characteristics associated with a first printed circuit board (PCB), said first PCB comprising a plurality of edge connectors configured to electrically interface with a plurality of pin-socket connections adapted to receive a DUT;
using a prototype load board to design a connection layout between said first PCB and a test head of a circuit tester, said prototype load board comprising:
said miniature load board removeably integrated therein;
a frame with mounting positions; and
a plurality of removable repositionable connectors for attachment to said frame and a plurality of flexible connections between said plurality of removable repositionable connectors and said plurality of edge connectors, said prototype load board configured to electrically couple said miniature load board to electrical connections formed on a test head surface; and

fabricating a second PCB based on said connection layout, said second PCB comprising a PCB mounting location for loading said first PCB during an operational mode thereof and permanent located connectors for connecting to said test head, wherein said first PCB comprises smaller dimensions relative to said second PCB.

16. The method described in claim 15 , wherein said characterizing electrical characteristics further comprises characterizing electrical characteristics associated with said first PCB in a test environment.

17. The method described in claim 16 , wherein said test environment is a client test environment.

18. The method described in claim 17 , wherein said client test environment further comprises using benchmark tests configured to measure signal characteristics between said plurality of edge connectors and said plurality of pin-socket connections.

19. The method described in claim 15 , wherein fabricating a second PCB further comprises generating traces that route final positions of said plurality of removable repositionable connectors stored within said frame to a final position of said DUT stored within said first PCB.

20. The method described in claim 15 , wherein said first PCB is a daughter board.

Assignees

• Advantest Corp

Inventors

• Lam Daniel

Classifications

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R1/07378 Primary

  using an intermediate adapter, e.g. space transformers (G01R1/07371 takes precedence) · CPC title

• G01R31/2889 Primary

  Interfaces, e.g. between probe and tester (G01R31/31905 and G01R1/07364 take precedence) · CPC title