Digital signal up-converting apparatus and related digital signal up-converting method

Patent metadata

Field	Value
Publication number	US-9917586-B2
Application number	US-201715611822-A
Country	US
Kind code	B2
Filing date	Jun 2, 2017
Priority date	May 21, 2013
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A digital signal up-converting apparatus includes: a clock generating circuit arranged to generate a reference clock signal; an adjusting circuit coupled to the clock generating circuit and arranged to generate a first clock signal and a second clock signal according to the reference clock signal; a baseband circuit coupled to the adjusting circuit for receiving the first clock signal, wherein the baseband circuit further generates a digital output signal according to the first clock signal; and a sampling circuit coupled to the adjusting circuit and the baseband circuit for receiving the second clock signal and the digital output signal, wherein the second clock signal and the digital output signal are non-overlapping; wherein the sampling circuit samples the digital output signal based on the second clock signal and then combines the sampled digital output signal in order to generate a combined digital signal.

First claim

The invention claimed is:

1. A digital signal up-converting apparatus, comprising:
a clock generating circuit, arranged to generate a reference clock signal;
an adjusting circuit, coupled to the clock generating circuit, arranged to generate a first clock signal and a plurality of second clock signals according to the reference clock signal;
a baseband circuit, coupled to the adjusting circuit, for receiving the first clock signal, wherein the baseband circuit generates a digital output signal according to the first clock signal; and
a sampling circuit, coupled to the adjusting circuit and the baseband circuit, for receiving the plurality of second clock signals and the digital output signal, wherein the plurality of second clock signals are non-overlapping;
wherein the sampling circuit samples the digital output signal based on at least one of the plurality of second clock signals and then combines the sampled digital output signal in order to generate a combined digital signal, and
wherein the first clock signal is a phase-adjusted clock signal of the reference clock signal and the at least one of the plurality of second clock signals is a duty cycle-adjusted clock signal of the reference clock signal.

2. The digital signal up-converting apparatus of claim 1 , wherein the clock generating circuit is arranged to generate a plurality of reference clock signals.

3. The digital signal up-converting apparatus of claim 2 , wherein the plurality of reference clock signals comprises at least four reference clock signals.

4. The digital signal up-converting apparatus of claim 1 , wherein the adjusting circuit is arranged to generate a plurality of first clock signals and the baseband circuit generates the digital output signal according to the plurality of first clock signals.

5. The digital signal up-converting apparatus of claim 4 , wherein the plurality of first clock signals comprises at least four first clock signals.

6. The digital signal up-converting apparatus of claim 1 , wherein the plurality of second clock signals comprises at least four second clock signals.

7. The digital signal up-converting apparatus of claim 1 , wherein the digital output signal comprises a plurality of digital output signals.

8. The digital signal up-converting apparatus of claim 7 , wherein the plurality of digital output signals comprises at least four digital output signals.

9. The digital signal up-converting apparatus of claim 1 , further comprising an amplifier, arranged to generate an amplified output signal according to the combined digital signal.

10. The digital signal up-converting apparatus of claim 1 , wherein the adjusting circuit comprises a phase adjusting circuit arranged to adjust a phase of the reference clock signal to generate the first clock signal.

11. The digital signal up-converting apparatus of claim 1 , wherein the adjusting circuit comprises a duty cycle adjusting circuit arranged to adjust a duty cycle of the reference clock signal to generate the plurality of second clock signals.

12. The digital signal up-converting apparatus of claim 1 , wherein the baseband circuit is arranged to delay baseband data to generate the digital output signal according to the first clock signal.

13. The digital signal up-converting apparatus of claim 1 , wherein signal edges of the plurality of second clock signals are non-overlapping.

14. A method, comprising:
generating a reference clock signal;
generating a first clock signal and a plurality of second clock signals according to the reference clock signal;
generating digital output signals according to the first clock signal; and
sampling the digital output signals based on at least one of the plurality of second clock signals; and
combining the sampled digital output signals to generate a combined digital signal,
wherein the first clock signal is a phase-adjusted clock signal of the reference clock signal and the at least one of the plurality of second clock signals is a duty cycle-adjusted clock signal of the reference clock signal.

15. The method of claim 14 , further comprising generating an amplified output signal according to the combined digital signal.

16. The method of claim 14 , further comprising adjusting a phase of the reference clock signal to generate the first clock signal.

17. The method of claim 14 , further comprising adjusting a duty cycle of the reference clock signal to generate the plurality of second clock signals.

18. The method of claim 14 , further comprising delaying baseband data to generate the digital output signals according to the first clock signal.

19. The method of claim 14 , wherein signal edges of the plurality of second clock signals are non-overlapping.

20. The method of claim 14 , wherein the plurality of second clock signals comprises at least four second clock signals.

Assignees

• Mediatek Inc

Inventors

• Chen Yang-Chuan
• Wang Chi-Hsueh
• Chang Hsiang-Hui
• Lin Bo-Yu

Classifications

• H04L7/0037

  Delay of clock signal · CPC title

• H04L27/3444

  by applying a certain rotation to regular constellations · CPC title

• H04L25/08

  Modifications for reducing interference; Modifications for reducing effects due to line faults {; Receiver end arrangements for detecting or overcoming line faults} · CPC title

• H03F3/2178

  using more than one switch or switching amplifier in parallel or in series (H03F3/2173, H03F3/2175 take precedence) · CPC title

• H04L27/2067

  with more than two phase states (H04L27/2064 takes precedence) · CPC title