Multi-staged buck converter with efficient low power operation

Patent metadata

Field	Value
Publication number	US-9917510-B2
Application number	US-201615216640-A
Country	US
Kind code	B2
Filing date	Jul 21, 2016
Priority date	Jul 21, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A system and method of increasing the efficiency in multi-stage power converters by providing an open loop charge pump stage which reacts in part based on information from a closed loop multi-phase buck converter stage.

First claim

We claim:

1. A method of operating a two-staged DC/DC power converter comprising:
dividing an input voltage in a charge pump clocked according to a first frequency for a clock signal to produce a charge pump output voltage;
while the charge pump is clocked according to the first frequency, operating a multi-phase buck converter using each phase in a plurality of phases to convert the charge pump output voltage into a regulated buck converter output voltage responsive to an output load, each phase including an inductor, a high-side switch, and a low-side switch;
adjusting the clock signal to cycle at a second frequency lower than the first frequency;
clocking the charge pump according to the second frequency of the clock signal to divide the input voltage to produce the charge pump output voltage; and
while the charge pump is clocked according to the second frequency, operating the multi-phase buck converter with a reduced set of the phases to convert the charge pump output voltage into the regulated buck converter output voltage, wherein the reduced set of phases is less than the plurality of phases by a phase reduction, and wherein the second frequency is lower than the first frequency by a frequency reduction that is proportional to the phase reduction.

2. The method of claim 1 , wherein operating the multi-phase buck converter using each phase in the plurality of phases comprises operating the multi-phase buck converter with four phases.

3. The method of claim 1 , wherein the frequency reduction is linearly proportional to the phase reduction.

4. The method of claim 3 , wherein the phase reduction is a reduction of two phases, and wherein the second frequency is one-half of the first frequency.

5. The method of claim 3 , wherein the phase reduction is a reduction from four phases to one phase, and wherein the second frequency is one-fourth of the first frequency.

6. The method of claim 1 , wherein the frequency reduction is non-linearly proportional to the phase reduction.

7. The method of claim 1 , wherein the dividing the input voltage in the charge pump comprises substantially dividing the input voltage by two.

8. The method of claim 1 , wherein the dividing the input voltage in the charge pump comprises substantially dividing the input voltage by three.

9. The method of claim 1 , wherein the charge pump includes two stages, each having a flying capacitor, and wherein both the dividing of the input voltage in the charge pump clocked according to the first frequency and the clocking of the charge pump according to the second frequency of the clock signal to divide the input voltage both comprise operating the charge pump with both stages, the method further comprising:
dividing the input voltage in the charge pump using just one of the stages responsive to a determination that the multi-phase buck converter has entered a discontinuous conduction mode of operation.

10. The method of claim 9 , further comprising:
ceasing the clocking of the charge pump responsive to the charge pump output voltage exceeding a high voltage threshold while the charge pump operates using just one stage; and
resuming the clocking of the charge pump responsive to the charge pump output voltage being less than a low voltage threshold, wherein the low voltage threshold is less than the high voltage threshold.

11. A two-stage DC/DC power converter, comprising:
a charge pump configured to divide in input voltage into a charge pump output voltage responsive to clock signal;
a multi-phase buck converter having a plurality of phases, each phase including an inductor, a high-side switch, and a low-side switch; and
a controller configured to command the multi-phase buck converter to use each phase in the plurality of phases to convert the charge pump output voltage into a regulated buck converter output voltage while the charge pump is clocked according to a first frequency, wherein the controller is further configured to command the multi-phase buck converter to use a reduced set of the phases to convert the charge pump output voltage into the regulated buck converter output voltage while the charge pump is clocked according to a second frequency that is lower than the first frequency by a frequency reduction, and wherein the reduced set of phases is less than the plurality of phases by a phase reduction, and wherein the frequency reduction is proportional to the phase reduction.

12. The two-stage DC/DC power converter of claim 11 , wherein the plurality of phases is a plurality of four phases, and wherein the phase reduction is two phases, and wherein the second frequency is one-half of the first frequency.

13. The two-stage DC/DC power converter of claim 11 , wherein the plurality of phases is a plurality of four phases, and wherein the phase reduction is three phases, and wherein the second frequency is one-fourth of the first frequency.

14. The two-stage DC/DC power converter of claim 11 , wherein the charge pump is configured to divide the input voltage substantially by two to produce the charge pump output voltage.

15. The two-stage DC/DC power converter of claim 14 , wherein the input voltage substantially equals 10 volts, and wherein the charge pump output voltage substantially equals 5 volts.

16. The two-stage DC/DC power converter of claim 11 , wherein each high-side switch and each low-side switch comprises an NMOS transistor.

17. The two-stage DC/DC power converter of claim 11 , wherein the charge pump comprises two stages, each stage having a flying capacitor, and wherein the controller is further configured to control the charge pump to use just one stage responsive to a determination that the multi-phase buck converter has entered a discontinuous conduction mode of operation.

18. The two-stage DC/DC power converter of claim 11 , wherein the controller is further configured to control the one stage of the charge pump to skip pulses responsive to the charge pump output voltage exceeding a high voltage threshold.

19. The two-stage DC/DC power converter of claim 18 , wherein the controller is further configured to control the one stage of the charge pump to resume pulsing responsive to the charge pump output voltage dropping below a low voltage threshold that is less than the high voltage threshold.

20. The two-stage DC/DC power converter of claim 11 , wherein the charge pump is an open loop charge pump.

Assignees

• Dialog Semiconductor Uk Ltd

Inventors

• Ahmed Ershad
• Negru Sorin Laurentiu
• Ng Chi-Man
• Gherghescu Alin

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/1584 Primary

  with a plurality of power processing stages connected in parallel · CPC title

• H02M1/0054

  Transistor switching losses (periodically suspending operation of switching converter in low power mode H02M1/0035) · CPC title

• H02M1/0035

  using burst mode control · CPC title

• H02M3/072

  adapted to generate an output voltage whose value is lower than the input voltage · CPC title