Hot swap controller with individually controlled parallel current paths

Patent metadata

Field	Value
Publication number	US-9917437-B2
Application number	US-201514705489-A
Country	US
Kind code	B2
Filing date	May 6, 2015
Priority date	May 6, 2015
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

An apparatus comprises an input node, a power rail to power a circuit load, and multiple current paths coupled in parallel with each other between the input node and the power rail. Each current path respectively provides a sense output to indicate current in the path and a current switch having a control input to control the current in the path. A control circuit, coupled to each control input individually and to each sense output individually, controls the current in each path individually based on the indicated current therein after a non-zero input voltage is initially applied to the input node, such that all of the paths concurrently conduct current from the input node to the power rail and collectively cause a total inrush current and corresponding voltage at the power rail to gradually increase.

First claim

What is claimed is:

1. An apparatus comprising:
an input node;
a power rail to power a circuit load;
multiple current paths coupled in parallel with each other between the input node and the power rail, each current path respectively providing a sense output to indicate current in the path and including a current switch having a control input to control the current; and
a control circuit coupled to each control input individually and to each sense output individually, the control circuit configured to store data representing a curve that defines a gradually increasing desired current vs. time, periodically sense the current in each path, access a desired current defined by the data representing the curve corresponding to a time when the current is sensed, and adjust the current to match the desired current for the corresponding time, so as to control the current in each path individually based on the indicated current therein after a non-zero input voltage is initially applied to the input node, such that all of the paths concurrently conduct current from the input node to the power rail and collectively cause a total inrush current and corresponding voltage at the power rail to gradually increase.

2. The apparatus of claim 1 , wherein the control circuit is further configured to control the current in each path individually so that all of the currents gradually increase from zero to respective steady state currents concurrently and the inrush current and voltage at the power rail correspondingly gradually increase from zero to a steady state current and a steady state voltage near the non-zero input voltage to power the circuit load.

3. The apparatus of claim 2 , wherein the control circuit is further configured to control the current in each path individually so as to balance the currents relative to each other in accordance with a predetermined criterion.

4. The apparatus of claim 3 , wherein the predetermined balance criterion is that all of the currents in the paths are to be substantially the same while gradually increased.

5. The apparatus of claim 1 , wherein:
each current switch includes a respective field effect transistor (FET) having a source-drain path coupled between the input node and the power rail, and a gate to serve as the control input; and
the control circuit provides a respective one of multiple control voltages to the gate of each of the FETs to control the current through each of the FET source-drain paths individually.

6. The apparatus of claim 5 , wherein:
the control circuit is configured to provide different control voltages to the gates of the FETs to ensure the FETs conduct current concurrently.

7. The apparatus of claim 5 , wherein the control circuit is further configured to detect failures in the FETs individually after the non-zero input voltage is applied to the input node.

8. The apparatus of claim 7 , wherein to detect FET gate-source short failures, the control circuit is configured to:
monitor the gate voltage on each FET over time; and
if the monitored gate voltage on a given FET remains zero for a predetermine time period, declare that the given FET has a gate-source short failure.

9. The apparatus of claim 7 , wherein to detect FET source-drain short failures, the control circuit is configured to:
turn-off the FETs individually; and
if the indicated current in the path in which a given FET that is turned-off is non-zero, declare that the given FET has a drain-source failure.

10. The apparatus of claim 7 , wherein to detect FET source-drain break failures, the control circuit is configured to:
turn-on the FETs individually; and
if the indicated current in the path in which a given FET that is turned-on is near zero, declare that the given FET has a drain-source failure.

11. The apparatus of claim 5 , wherein:
each path respectively includes a sense resistor connected in series with the FET between the input node and the output power rail, such that a first end of the resistor is connected to the input node, a second end of the resistor is connected to the FET, and a voltage across the first end and the second end represents the sense output to indicate the current in the current path; and
the control circuit includes a single first sense input coupled to the input node and in common to the first ends of the sense resistors, the control circuit having multiple second sense inputs connected individually to respective ones of the second ends of the sense resistors.

12. The apparatus of claim 5 , further comprising:
a respective sense FET paired with each respective FET, each sense FET to mirror the current in the respective FET, wherein the sense output includes a first tap on a source of the sense FET and a second tap on a source of the respective FET.

13. The apparatus of claim 1 , further comprising:
a circuit board including a circuit board connector to mate with a complimentary connector of a chassis to retain the circuit board, the circuit board connector including power pins to receive power from complimentary power pins of the chassis connector, and wherein:
the circuit load includes circuitry on the circuit board; and
the input node, the power rail, the multiple current paths, and the control circuit collectively comprise a hot swap controller on the circuit board, and the input node is connected to at least one of the power pins of the circuit board connector to receive power from the at least one of the power pins when the circuit board and chassis connectors are mated.

14. The apparatus of claim 13 , further comprising a trigger circuit to detect the non-zero input voltage initially applied to the input node when the circuit board is initially mated to the chassis, and to produce a trigger signal when the non-zero voltage is detected, wherein the control circuit is configured to perform the control of the current in each path individually responsive to the trigger signal.

15. The apparatus of claim 1 , wherein the control circuit is configured to store the curve as a series of points each defined by a “desired current, time” pair, and the control circuit is further configured to: when the sensed current is less than or greater than the desired current, increase or decrease the current do drive the current closer to the desired current.

16. A method comprising:
in hot swap controller including an input node, a power rail coupled to a circuit load, and multiple current paths coupled in parallel with each other between the input node and the power rail, each current path respectively including a sense output to indicate current in the path and a current switch having a control input to control the current in the path;
storing data representing a curve that defines a gradually increasing desired current vs. time; and
receiving a step-up in voltage from a zero potential to a non-zero potential at the input node and, responsive to the step-up in voltage, periodically:
sensing current in each of the current paths individually;
accessing a desired current defined by the data representing the curve corresponding to a time when the current is sensed; and
adjusting the current to match the desired current for the corresponding time such that the adjusting results in controlling the current in each path individually based on the current sensed therein, to cause all of the paths to concurrently conduct current from the input node to the power rail and collectively cause an inrush current and corresponding voltage at the power rail to gradually increase.

17. The method of claim 16 , wherein the controlling incl

Assignees

• Cisco Tech Inc

Inventors

• Sun Yang
• Gan Zhongmin
• Chen Bruce
• Bai Yun
• Wang Nan

Classifications

• H02H9/004 Primary

  in connection with live-insertion of plug-in units (involving communication with a central processing unit G06F13/40) · CPC title