Semiconductor devices and methods of manufacture thereof

Patent metadata

Field	Value
Publication number	US-9917191-B2
Application number	US-201514935067-A
Country	US
Kind code	B2
Filing date	Nov 6, 2015
Priority date	Aug 1, 2007
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Semiconductor devices and methods of manufacture thereof are disclosed. In a preferred embodiment, a method of manufacturing a semiconductor device includes providing a semiconductor wafer, forming a gate dielectric over the semiconductor wafer, and forming a gate over the gate dielectric. At least one recess is formed in the semiconductor wafer proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate. The at least one recess in the semiconductor wafer is filled with a semiconductive material.

First claim

What is claimed is:

1. A semiconductor device comprising:
a gate dielectric over a semiconductor substrate;
a gate over the gate dielectric;
at least one recess in the semiconductor substrate proximate the gate and the gate dielectric, at least a portion of the at least one recess extending beneath the gate, wherein the at least one recess in the semiconductor substrate is filled with a semiconductive material of a first doping type, and the semiconductive material comprising a first semiconductor element and a second semiconductor element and being doped with a dopant of the first doping type; and
a doped region of a second doping type disposed completely within the semiconductive material, the second doping type being opposite to the first doping type, the doped region comprising a source/drain of a transistor, wherein a concentration of the dopant at a bottom surface and sides of the at least one recess is greater than a concentration of the dopant at a central region comprising the doped region.

2. The device according to claim 1 , wherein the at least one recess extends by at least 50 Angstroms beneath the gate on at least one side.

3. The device according to claim 1 , wherein the semiconductive material filling the at least one recess comprises a compound semiconductor material.

4. A semiconductor device comprising:
a gate dielectric over a semiconductor substrate;
a gate disposed over the gate dielectric;
a recess in the semiconductor substrate proximate the gate, wherein the recess overlaps directly under a portion of the gate;
an epitaxial semiconductive material disposed in the recess, the epitaxial semiconductive comprising a first doping type;
a deep source/drain region of a second doping type, the second doping type being opposite to the first doping type, the deep source/drain region being fully disposed within the epitaxial semiconductive material and being a source/drain of a transistor; and
a shallow source/drain region of the second doping type extending laterally from the deep source/drain region, the shallow source/drain region being fully disposed within the epitaxial semiconductive material and comprising a p/n junction, wherein the p/n junction is disposed fully within the recess that is filled with the epitaxial semiconductive material.

5. The device according to claim 4 , further comprising a silicide disposed over at least the epitaxial semiconductive material.

6. A transistor comprising:
a channel region disposed within a substrate, the channel region comprising a first side and a second side opposite the first side;
a gate dielectric disposed over the channel region;
a gate disposed over the gate dielectric, the gate and the gate dielectric having sidewalls;
at least one sidewall spacer disposed over the sidewalls of the gate and the gate dielectric;
a recess disposed in the substrate and comprising a semiconductive material comprising a first semiconductor element and a second semiconductor element, wherein a portion of the semiconductive material in the recess is disposed beneath a portion of the gate and doped with a first dopant having a first doping type;
a source region disposed completely within the semiconductive material, wherein the source region contacts the first side of the channel region;
a drain region disposed completely within the semiconductive material, wherein the drain region contacts the second side of the channel region, the source region and the drain region are doped with a second dopant having a second doping type opposite the first dopant type; and, wherein a concentration of the first dopant at a bottom surface of the source region is greater than a concentration of the first dopant at a central region of the source and drain regions.

7. The transistor according to claim 6 , wherein the portion of the semiconductive material disposed beneath the portion of the gate extends beneath the gate by about 50 Angstroms on the first side and the second side of the channel region.

8. The transistor according to claim 6 , wherein the transistor comprises a p channel metal oxide semiconductor (PMOS) field effect transistor (FET).

9. The transistor according to claim 8 , wherein the semiconductive material is configured to increase a tensile stress of the source region and the drain region.

10. The transistor according to claim 6 , wherein the transistor comprises an n channel metal oxide semiconductor (NMOS) field effect transistor (FET).

11. The transistor according to claim 9 , wherein the semiconductive material is configured to increase a compressive stress of the source region and the drain region.

12. The transistor according to claim 6 , wherein the first dopant of the semiconductive material comprises a greater concentration proximate a side surface of the source region and the drain region than proximate a central region of the source region and the drain region.

13. A complementary metal oxide semiconductor (CMOS) device including the transistor of claim 6 .

14. The device according to claim 1 , wherein the at least one recess comprises a sidewall having a curved surface under the gate.

15. The device according to claim 4 , wherein the recess comprises a sidewall having a curved surface under the gate.

16. The transistor according to claim 6 , wherein the recess comprises a sidewall having a curved surface under the gate.

Assignees

• Infineon Technologies Ag

Inventors

• Eller Manfred
• Han Jin-Ping

Classifications

• H01L29/66636

  Electricity · mapped topic

• H01L29/6659

  Electricity · mapped topic

• H01L29/7833

  Electricity · mapped topic

• H01L21/823807

  Electricity · mapped topic

• H01L29/7843

  Electricity · mapped topic