Array substrate and method of mounting integrated circuit using the same

Patent metadata

Field	Value
Publication number	US-9917113-B2
Application number	US-201715429411-A
Country	US
Kind code	B2
Filing date	Feb 10, 2017
Priority date	Jun 17, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

An array substrate including a display area and a non-display area surrounding the display area. The non-display area includes a pad portion including one or more first pads that each have a parallelogram shape.

First claim

What is claimed is:

1. An electronic device comprising:
an array substrate;
a pad portion disposed on the array substrate; and
an integrated circuit disposed on the pad portion and comprising a bump portion;
wherein:
the pad portion comprises a first sub-pad unit comprising a first pad having a parallelogram shape and a second sub-pad unit comprising a second pad having a parallelogram shape, and the first pad and the second pad are symmetrically arranged with respect to a first imaginary line that divides the pad portion; and
the pad portion is electrically connected to the bump portion.

2. The electronic device of claim 1 , wherein the bump portion comprises a first sub-bump unit comprising a first bump having a parallelogram shape and a second sub-bump unit comprising a second bump having a parallelogram shape.

3. The electronic device of claim 2 , wherein the first bump and the second bump are symmetrically arranged with respect to a second imaginary line that divides the bump portion.

4. The electronic device of claim 2 , wherein a shape of the first bump corresponds to a shape of the first pad, and a shape of the second bump corresponds to a shape of the second pad.

5. The electronic device of claim 2 , wherein the first pad is electrically connected to the first bump and the second pad is electrically connected to the second bump.

6. The electronic device of claim 2 , wherein an area of the first pad is larger than an area of the first bump.

7. The electronic device of claim 2 , wherein the pad portion further comprises a third sub-pad unit comprising a third pad having a rectangular shape and disposed between the first sub-pad unit and the second sub-pad unit.

8. The electronic device of claim 7 , wherein the bump portion further comprises a third sub-bump unit comprising a third bump having a rectangular shape and disposed between the first sub-bump unit and the second sub-bump unit.

9. The electronic device of claim 2 , wherein:
the first bump comprises a first region and a second region; and
the first region overlaps the first pad and the second region does not overlap the first pad.

10. The electronic device of claim 2 , wherein the first bump completely overlaps the first pad.

11. An electronic device comprising:
an array substrate;
a pad portion disposed on the array substrate; and
an integrated circuit disposed on the pad portion and comprising a bump portion;
wherein:
the pad portion comprises a first sub-pad unit comprising first pads each having a parallelogram shape; and
the bump portion comprises a first sub-bump unit comprising first bumps each having a parallelogram shape, and a second sub-bump unit comprising second bumps each having a parallelogram shape.

12. The electronic device of claim 11 , wherein:
the pad portion further comprises a second sub-pad unit comprising second pads each having a parallelogram shape; and
the first pads and the second pads are symmetrically arranged with respect to a first imaginary line that divides the pad portion.

13. The electronic device of claim 12 , wherein:
the bump portion further comprises a second sub-bump unit comprising second bumps each having a parallelogram shape; and
the first bumps and the second bumps are symmetrically arranged with respect to a second imaginary line that divides the pad portion.

14. The electronic device of claim 12 , wherein:
each of the first pads have an inclination angle defined as an acute internal angle between the short sides and the long sides of each of the first pads; and
inclination angles of the first pads increase as the first pads get closer to the first imaginary line.

15. The electronic device of claim 12 , wherein:
each of the second pads have an inclination angle defined as an acute internal angle between the short sides and the long sides of each of the second pads; and
inclination angles of the second pads increase as the second pads get closer to the first imaginary line.

16. The electronic device of claim 12 , wherein the pad portion further comprises a third sub-pad unit comprising a third pad having a rectangular shape and disposed between the first sub-pad unit and the second sub-pad unit.

Assignees

• Samsung Display Co Ltd

Inventors

• Lee Dae Geun

Classifications

• H10W72/9445

  Top-view layouts, e.g. mirror arrays · CPC title

• H10W72/07223

  Active alignment, e.g. using optical alignment using marks or sensors · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H05K2201/09709

  Staggered pads, lands or terminals; Parallel conductors in different planes · CPC title

• H05K1/189

  characterised by the use of flexible or folded printed circuits · CPC title