Semiconductor device having staggered pillars

Patent metadata

Field	Value
Publication number	US-9917094-B2
Application number	US-201514920223-A
Country	US
Kind code	B2
Filing date	Oct 22, 2015
Priority date	Sep 5, 2012
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Provided is a semiconductor device including gate structures provided on a substrate, a separation insulating layer interposed between the gate structures, and a plurality of cell pillars connected to the substrate through each gate structure. Each gate structure may include horizontal electrodes vertically stacked on the substrate, and an interval between adjacent ones of the cell pillars is non-uniform.

First claim

What is claimed is:

1. A semiconductor memory device comprising:
a plurality of horizontal electrodes including an upper selection gate and cell gates below the upper selection gate;
a plurality of insulating patterns alternatingly stacked with the plurality of horizontal electrodes; and
an array of pillars formed in the plurality of insulating patterns and the plurality of horizontal electrodes, the array of pillars comprising:
a first column of pillars disposed along a first direction when viewed from a top of the semiconductor memory device;
a second column of pillars disposed along the first direction and adjacent to the first column of pillars, and staggered with respect to the first column of pillars, and
a third column of pillars disposed along the first direction and adjacent to the second column of pillars such that the second column of pillars is between the first column of pillars and the third column of pillars, the third column of pillars staggered with respect to the second column of pillars,

wherein a first pitch between a first pillar of the first column and a second pillar of the second column nearest to the first pillar is greater than a second pitch between the second pillar and a third pillar of the third column adjacent to the second pillar, and
wherein the first column of pillars, the second column of pillars, and the third column of pillars are coupled to a same upper selection gate.

2. The semiconductor device of claim 1 , wherein the upper selection gate and the cell gates extend along a second direction perpendicular to the first direction when viewed from the top of the semiconductor device, and
wherein the first pillar, the second pillar, and the third pillar are disposed along a third direction when viewed from the top of the semiconductor device, the third direction crossing the first direction and the second direction.

3. The semiconductor device of claim 2 , wherein the first direction, the second direction, and the third direction are directions in a same plane.

4. The semiconductor device of claim 1 , wherein the first group of pillars include a fourth pillar nearest to the first pillar,
wherein an interval between the first pillar and the fourth pillar is greater than an interval between the first pillar and the second pillar.

5. A semiconductor memory device comprising:
a plurality of horizontal electrodes including an upper selection gate and cell gates below the upper selection gate; and
an array of pillars formed in the plurality of horizontal electrodes, the array of pillars comprising a first column, a second column and a third column disposed adjacent to one another,
wherein each of the first, the second and the third columns comprises pillars disposed along a first direction when viewed from a top of the semiconductor memory device and coupled to a same upper selection gate,
wherein the second column is staggered with the first column and the third column,
wherein a first pitch between a first pillar of the first column and a second pillar of the second column nearest to the first pillar is greater than a second pitch between the second pillar and a third pillar of the third column nearest to the second pillar,
wherein the first pillar, the second pillar, and the third pillar are disposed along a third direction crossing the first direction.

6. The semiconductor device of claim 5 , wherein the first group of pillars include a fourth pillar nearest to the first pillar,
wherein an interval between the first pillar and the fourth pillar is greater than an interval between the first pillar and the second pillar.

7. The semiconductor device of claim 5 , wherein the upper selection gate and the cell gates extend along a second direction when viewed from the top of the semiconductor device , the second direction being perpendicular to the first direction, and
wherein the first direction, the second direction, and the third direction are directions in a same plane.

Assignees

• Lee Wookhyoung
• Chun Jongsik
• Shim Sunil
• Ahn Jaeyoung
• Lee Juyul
• Hwang Kihyun
• Kim Hansoo
• Lee Woonkyung
• Jang Jaehoon
• Cho Wonseok
• Samsung Electronics Co Ltd

Inventors

• Lee Wookhyoung
• Chun Jongsik
• Shim Sunil
• Ahn Jaeyoung
• Lee Juyul
• Hwang Kihyun
• Kim Hansoo
• Lee Woonkyung
• Jang Jaehoon
• Cho Wonseok

Classifications

• H10W72/00

  Interconnections or connectors in packages · CPC title

• G11C5/06

  Arrangements for interconnecting storage elements electrically, e.g. by wiring · CPC title

• H01L27/11582

  Electricity · mapped topic

• H01L27/0207

  Electricity · mapped topic

• G11C7/00

  Arrangements for writing information into, or reading information out from, a digital store (G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413) · CPC title