Semiconductor device having stacked chips, a re-distribution layer, and penetration electrodes

Patent metadata

Field	Value
Publication number	US-9917066-B2
Application number	US-201414332394-A
Country	US
Kind code	B2
Filing date	Jul 16, 2014
Priority date	Feb 9, 2012
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A lamination structure includes a first semiconductor chip and a second semiconductor chip stacked via a bonding section so that a rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip. At least a part of a side surface of the first semiconductor chip are covered with a first resin, a distribution layer is formed on the plane formed of the main surface of the first semiconductor chip and a surface of the first resin. At least part of electrodes existing in the main surface of the second semiconductor chip is electrically connected to at least part of first external electrodes formed on the distribution layer via the penetration electrodes that penetrate the first semiconductor chip.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first semiconductor chip including a main surface which has a distribution layer as an outermost layer and an element, a rear surface opposite the main surface, and penetration electrodes penetrating the main surface and the rear surface; and
a second semiconductor chip including a main surface having an element and a rear surface opposite the main surface, wherein
the first semiconductor chip and the second semiconductor chip are stacked via bonding sections so that the rear surface of the first semiconductor chip faces the main surface of the second semiconductor chip,
each of the bonding sections includes a first electrode on the rear surface of the first semiconductor chip and a second electrode on the main surface of the second semiconductor chip,
at least a part of a side surface of the first semiconductor chip is covered with a first resin,
a re-distribution layer is produced on a plane formed by a surface of the distribution layer and a surface of the first resin,
the surface of the distribution layer and the surface of the first resin are both parallel to the main surface of the first semiconductor chip,
the re-distribution layer contacts a wiring being included in the distribution layer,
an inter-layer insulating film is included in the distribution layer,
a boundary line between the inter-layer insulating film and the first resin is formed on an extended line of a side surface of the first semiconductor chip, and formed on a plane formed by the surface of the distribution layer and the surface of the first resin, and
at least a part of electrodes existing on the main surface of the second semiconductor chip is electrically connected to at least a part of first external electrodes via the penetration electrodes penetrating the first semiconductor chip, the first external electrodes being formed on the redistribution layer.

2. The semiconductor device of claim 1 , wherein an area of the main surface of the first semiconductor chip is different from an area of the main surface of the second semiconductor chip.

3. The semiconductor device of claim 1 , wherein an area of the main surface of the first semiconductor chip is smaller than an area of the main surface of the second semiconductor chip.

4. The semiconductor device of claim 1 , wherein a thickness of the first semiconductor chip is different from a thickness of the second semiconductor chip.

5. The semiconductor device of claim 1 , wherein the first semiconductor chip is thinner than the second semiconductor chip.

6. The semiconductor device of claim 1 , wherein the first external electrodes are disposed on the re-distribution layer in both regions of the main surface of the first semiconductor chip and the surface of the first resin.

7. The semiconductor device of claim 1 , wherein the first external electrodes are disposed on the re-distribution layer on only the surface of the first resin.

8. The semiconductor device of claim 1 , wherein the bonding sections between the first semiconductor chip and the second semiconductor chip are disposed inside the first external electrode that is disposed in an innermost side, of the first external electrodes.

9. The semiconductor device of claim 1 , wherein the penetration electrodes are disposed inside the first external electrode that is disposed in an innermost side, of the first external electrodes.

10. The semiconductor device of claim 1 , wherein a bonding pitch between the bonding sections between the first semiconductor chip and the second semiconductor chip is equal to a pitch between the penetration electrodes.

11. The semiconductor device of claim 1 , wherein the first resin is formed also so as to cover a part of the rear surface of the first semiconductor chip and a periphery of the second semiconductor chip.

12. The semiconductor device of claim 1 , wherein the first resin is formed so as to cover a part of the rear surface of the first semiconductor chip and the main surface of the second semiconductor chip, and expose at least a part of the rear surface or a side surface of the second semiconductor chip.

13. The semiconductor device of claim 1 , wherein two facing side surfaces of the first semiconductor chip are exposed from the first resin.

14. The semiconductor device of claim 1 , further comprising a second resin covering a peripheral region of the bonding sections between the first semiconductor chip and the second semiconductor chip.

15. The semiconductor device of claim 1 , wherein a re-distribution layer is formed on the rear surface of the first semiconductor chip.

16. The semiconductor device of claim 1 , wherein a minimum pitch between the first external electrodes is 150 μm or more.

17. The semiconductor device of claim 1 , further comprising a wiring board having an electric wiring interconnecting a front surface and a rear surface of the wiring board, the first external electrodes being connected to the electric wiring on a front surface side of the wiring board, external connection electrodes being disposed on a rear surface side of the wiring board, wherein a minimum pitch between the external connection electrodes is 300 μm or more.

18. The semiconductor device of claim 1 , wherein a plurality of second semiconductor chips are stacked.

19. The semiconductor device of claim 18 , wherein of the stacked second semiconductor chips, a rear surface side of the second semiconductor chip formed on an uppermost layer is exposed from the first resin.

20. The semiconductor device of claim 1 , wherein
the first semiconductor chip is a logic chip having a logic circuit in an element region, and the second semiconductor chip is a memory chip having a memory circuit in an element region.

21. The semiconductor device of claim 1 , wherein the first electrode is directly in contact with the second electrode.

22. The semiconductor device of claim 1 , wherein the first electrode is in contact with at least one of the penetration electrodes.

Assignees

• Panasonic Corp

Inventors

• Aoi Nobuo
• Sasago Masaru
• Mori Yoshihiro
• Kawabata Takeshi
• Yui Takashi
• Fujii Toshio

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W90/28

  the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape · CPC title