Methods and apparatus for providing an interposer for interconnecting semiconductor chips

Patent metadata

Field	Value
Publication number	US-9917045-B2
Application number	US-201615287163-A
Country	US
Kind code	B2
Filing date	Oct 6, 2016
Priority date	Jan 31, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.

First claim

The invention claimed is:

1. An interposer for interconnecting one or more semiconductor chips with a substrate in a semiconductor package, the interposer comprising:
a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1);
a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2);
an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, wherein the interface is formed from an intermediate glass material having a melting temperature lower than melting temperatures of the first and second glass substrates; and
at least one via extending from the first major surface of the first glass substrate to the second major surface of the second glass substrate,
wherein CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the substrate.

2. The interposer of claim 1 , wherein 1≤CTE1 ppm/° C.≤10 and 5≤CTE2 ppm/° C.≤15.

3. The interposer of claim 1 , wherein 3≤CTE1 ppm/° C.≤5 and 8≤CTE2 ppm/° C.≤10.

4. A semiconductor package comprising:
the interposer of claim 1 ;
at least one semiconductor chip coupled to a first surface of the interposer; and
a substrate coupled to a second surface of the interposer.

5. An interposer for interconnecting one or more semiconductor chips with a substrate in a semiconductor package, the interposer comprising:
a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1);
a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2);
a third glass substrate having first and second opposing major surfaces, the third glass substrate having a third coefficient of thermal expansion (CTE3); and
at least one via extending from the first major surface of the first glass substrate to the second major surface of the third glass substrate,
a first intermediate glass material disposed between the second major surface of the first glass substrate and the first major surface of the second glass substrate, the first intermediate glass material having a melting temperature lower than melting temperatures of the first and second glass substrates; and
a second intermediate glass material disposed between the second major surface of the second glass substrate and the first major surface of the third glass substrate, the second intermediate glass material having a melting temperature lower than melting temperatures of the second and third glass substrates, wherein:
the first and second glass substrates are fused by the first intermediate glass material such that the second major surface of the first glass substrate is connected to the first major surface of the second glass substrate,
the second and third glass substrates are fused by the second intermediate glass material such that the second major surface of the second glass substrate is connected to the first major surface of the third glass substrate, and
the first major surface of the first glass substrate is adapted to engage the one or more semiconductor chips, and the second major surface of the third glass substrate is adapted to engage the substrate.

6. The interposer of claim 5 , wherein CTE1 is less than CTE2, and CTE3 is less than CTE2.

7. The interposer of claim 6 , wherein 1≤CTE1 ppm/° C.≤10; 5≤CTE2 ppm/° C.≤15; and 1≤CTE3 ppm/° C.≤10.

8. The interposer of claim 6 , wherein 3≤CTE1 ppm/° C.≤5; 8≤CTE2 ppm/° C.≤10; and 3≤CTE3 ppm/° C.≤5.

9. The interposer of claim 5 , wherein CTE1 is less than CTE2, and CTE2 is less than CTE3.

10. The interposer of claim 9 , wherein 1≤CTE1 ppm/° C.≤10; 3≤CTE2 ppm/° C.≤12; and 5≤CTE3 ppm/° C.≤15.

11. The interposer of claim 9 , wherein 3<CTE1 ppm/° C.≤5; 5≤CTE2 ppm/° C.≤8; and 8≤CTE3 ppm/° C.≤10.

12. A semiconductor package comprising:
the interposer of claim 5 ;
at least one semiconductor chip coupled to a first surface of the interposer; and
a substrate coupled to a second surface of the interposer.

Assignees

• Corning Inc

Inventors

• Chaparala Satish Chandra
• Pollard Scott Christopher

Classifications

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/721

  of bump connectors · CPC title

• H10W90/22

  the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL · CPC title

• H10W72/07254

  changes in dispositions · CPC title