Liquid crystal display device
US-2015179121-A1 · Jun 25, 2015 · US
US9916801B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9916801-B2 |
| Application number | US-201514743941-A |
| Country | US |
| Kind code | B2 |
| Filing date | Jun 18, 2015 |
| Priority date | Oct 10, 2014 |
| Publication date | Mar 13, 2018 |
| Grant date | Mar 13, 2018 |
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A pixel structure, array substrate, display panel, display device, and driving method of the display device are provided. The pixel structure includes a plurality of data lines and a plurality of scan lines; a plurality of pixel units formed by intersecting the data lines with the scan lines. Each of the pixel units corresponds to one of the data lines and one of the scan lines; and the pixel unit includes a pixel electrode and a thin film transistor therein. In one of two adjacent columns of pixel units, a pixel electrode of each pixel unit is electrically connected with a thin film transistor of the pixel unit; and in the other one of the two adjacent columns of pixel units, a pixel electrode of each pixel unit in a row is electrically connected with a thin film transistor of a pixel unit in an adjacent row.
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We claim: 1. A pixel structure, comprising: a plurality of data lines and a plurality of scan lines; and a plurality of pixel units formed by intersecting the plurality of data lines with the plurality of scan lines, wherein each of the plurality of pixel units corresponds to one of the plurality of data lines and one of the plurality of scan lines, and each of the plurality of pixel units comprises a pixel electrode and a thin film transistor therein, the thin film transistor comprises a gate electrode, a drain electrode, and a source electrode, the plurality of pixel units are arranged in columns, only one of the columns is arranged between every two adjacent ones of the plurality of data lines, and only one of the plurality of data lines is arranged between every two adjacent ones of the columns of pixel units, wherein the source electrodes of the thin film transistors of all pixel units in a same column are electrically connected to a same data line, wherein the plurality of pixel units comprises a first column of pixel units and a second column of pixel units adjacent to the first column of pixel units, the pixel electrode and the thin film transistor in a same pixel unit of the first column are electrically connected, and the second column of pixel units includes a first pixel unit and a second pixel unit adjacent the first pixel unit, the pixel electrode of the first pixel unit crosses over the scan line which is electrically connected with the thin film transistor of the second pixel unit, and the pixel electrode of the first pixel unit is electrically connected to the thin film transistor of the second pixel unit. 2. The pixel structure of claim 1 , wherein the first column of pixel units is an odd-numbered column, and the second column of pixel units is an even-numbered column. 3. The pixel structure of claim 1 , wherein the first column of pixel units is an even-numbered column, and the second column of pixel units is an odd-numbered column. 4. The pixel structure of claim 1 , further comprising a common electrode located between the pixel electrode and a film layer where a source electrode and a drain electrode of the thin film transistor electrically connected with the pixel electrode are located, and the common electrode is insulated from the pixel electrode and the film layer. 5. The pixel structure of claim 1 , wherein the plurality of pixel units are arranged in a staggered way or as a matrix. 6. A display device, comprising a pixel structure, with the pixel structure comprising: a plurality of data lines and a plurality of scan lines; and a plurality of pixel units formed by intersecting the plurality of data lines with the plurality of scan lines, wherein each of the pixel units corresponds to one of the plurality of data lines and one of the plurality of scan lines; and each of the plurality of pixel units comprises a pixel electrode and a thin film transistor therein, the thin film transistor comprises a gate electrode, a drain electrode, and a source electrode, the plurality of pixel units are arranged in columns, only one of the columns is arranged between every two adjacent ones of the plurality of data lines, and only one of the plurality of data lines is arranged between every two adjacent ones of the columns of pixel units, wherein the source electrodes of the thin film transistors of all pixel units in a same column are electrically connected to a same data line, wherein the plurality of pixel units comprises a first column of pixel units and a second column of pixel units adjacent to the first column of pixel units, the pixel electrode and the thin film transistor in a same pixel unit of the first column are electrically connected, and the second column of pixel units includes a first pixel unit and a second pixel unit adjacent the first pixel unit, the pixel electrode of the first pixel unit crosses over the scan line that is electrically connected with the thin film transistor of the second pixel unit and the pixel electrode of the first pixel unit is electrically connected to the thin film transistor of the second pixel unit. 7. The pixel structure of claim 1 , wherein every two adjacent rows of pixel units are separated by a corresponding one of the plurality of scan lines. 8. The pixel structure of claim 1 , wherein the thin film transistor of the first pixel unit and the thin film transistor of the second pixel unit are electrically connected to a same one of the plurality of data lines. 9. The display device of claim 6 , wherein every two adjacent rows of pixel units are separated by a corresponding one of the plurality of scan lines. 10. The display device of claim 6 , wherein the thin film transistor of the first pixel unit and the thin film transistor of the second pixel unit are electrically connected to a same one of the plurality of data lines.
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Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title
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