Phase algebra for analysis of hierarchical designs

Patent metadata

Field	Value
Publication number	US-9916407-B2
Application number	US-201514631539-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Dec 5, 2013
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A design tool can implement phase algebra based design evaluation to evaluate a circuit design with a compact representation of waveforms without simulating the individual waveforms. The tool can determine whether module instances of a register level circuit design share a common usage, each instance being associated with a mapping. Two instances share a common usage if a sequence of signal transition representations received by the first instance can be mapped using a first mapping to the same common sequence of signal transition representations as a mapping of another sequence of signal transition representations received by the second instance using a second mapping. A result sequence of signal transition representations was generated by a previous propagation of the common sequence through the common usage. If the two instances share the common usage, the result sequence is mapped to an output sequence for the second instance using the second mapping.

First claim

What is claimed is:

1. A computer program product for evaluation of a circuit design represented in register transfer level code and having a compact representation of waveforms, where the evaluation avoids simulation of the waveforms, the computer program product comprising:
a non-transitory computer readable storage medium having program instructions stored thereon, the program instructions executable on one or more processors, the program instructions comprising
instructions to determine, by a circuit evaluator operating via the one or more processors, a first mapping associated with a first instance of a first module of the circuit design represented in the register transfer level code and a second mapping associated with a second instance of the first module, wherein
the first mapping is for mapping a first input sequence of signal transition representations received by the first instance to a common sequence of signal transition representations, and
the second mapping is for mapping a second input sequence of signal transition representations received by the second instance to the common sequence;

instructions to determine, by a circuit evaluator operating via the one or more processors, whether the first instance and the second instance share a common usage, wherein
the common usage is associated with a result sequence of signal transition representations that was generated by a previous propagation of the common sequence through the common usage, and
each signal transition representation represents a non-deterministic transition from a previous signal state to a set of one or more possible signal states; and

instructions to, in response to a determination that the first instance and the second instance share the common usage, map the result sequence of signal transition representations to an output sequence of signal transition representations for the second instance using the second mapping.

2. The computer program product of claim 1 , wherein the previous propagation of the mapped first input sequence comprises,
propagation of the common sequence through the common usage to generate the result sequence of signal transition representations, wherein
the result sequence of signal transition representations is for mapping to a first output sequence of signal transition representations for the first instance using the first mapping, and
the result sequence of signal transition representations is for mapping to a second output sequence of signal transition representations for the second instance using the second mapping.

3. The computer program product of claim 1 , wherein
the first mapping maps one or more of:
a clock of the first input sequence to a clock of the common sequence, and
a mode of the first input sequence to a mode of the common sequence.

4. The computer program product of claim 1 , wherein
the common sequence is generated based on the first mapping prior to the determination of whether the first instance and the second instance share the common usage.

5. The computer program product of claim 1 , wherein program instructions to determine whether the first instance and the second instance share the common usage
comprise program instructions to,
determine a plurality of second mapping candidates for mapping the second input sequence to the common sequence, and
determine the second mapping from the plurality of second mapping candidates.

6. The computer program product of claim 5 , further comprising program instructions to,
eliminate one or more of the plurality of second mapping candidates prior to said determining the second mapping from the plurality of second mapping candidates.

7. An apparatus comprising:
one or more processors; and
a non-transitory computer readable storage medium having stored thereon program instructions executable by the one or more processors, to cause the apparatus to evaluate a circuit design represented in register transfer level code with compact representation of waveforms, where the evaluation avoids simulation of the waveforms, the program instructions comprising,
instructions to determine, by at least one of the processors, a first mapping associated with a first instance of a first module of the circuit design represented in register transfer level code and a second mapping associated with a second instance of the first module, wherein
the first mapping is for mapping a first input sequence of signal transition representations received by the first instance to a common sequence of signal transition representations,
the second mapping is for mapping a second input sequence of signal transition representations received by the second instance to the common sequence;

determine, by at least one of the processor, whether the first instance and the second instance share a common usage, wherein
the common usage is associated with a result sequence of signal transition representations that was generated by a previous propagation of the common sequence through the common usage, and
each signal transition representation represents a non-deterministic transition from a previous signal state to a set of one or more possible signal states; and

in response to a determination that the first instance and the second instance share the common usage, map the result sequence of signal transition representations to an output sequence of signal transition representations for the second instance using the second mapping.

8. The apparatus of claim 7 , wherein the previous propagation of the mapped first input sequence comprises,
propagation of the common sequence through the common usage to generate the result sequence of signal transition representations, wherein
the result sequence of signal transition representations is for mapping to a first output sequence of signal transition representations for the first instance using the first mapping, and
the result sequence of signal transition representations is for mapping to a second output sequence of signal transition representations for the second instance using the second mapping.

9. The apparatus of claim 7 , wherein
the first mapping maps one or more of:
a clock of the first input sequence to a clock of the common sequence, and
a mode of the first input sequence to a mode of the common sequence.

10. The apparatus of claim 7 , wherein
the common sequence is generated based on the first mapping prior to the determination of whether the first instance and the second instance share the common usage.

11. The apparatus of claim 7 , wherein program instructions executable to determine whether the first instance and the second instance share the common usage comprise program instructions executable to,
determine a plurality of second mapping candidates for mapping the second input sequence to the common sequence, and
determine the second mapping from the plurality of second mapping candidates.

Assignees

• IBM

Inventors

• Drasny Gabor
• Meil Gavin B

Classifications

• G06F30/396

  Clock trees · CPC title

• G06F2119/12

  Timing analysis or timing optimisation · CPC title

• G06F30/35

  Delay-insensitive circuit design, e.g. asynchronous or self-timed · CPC title

• G06F30/3323

  using formal methods, e.g. equivalence checking or property checking · CPC title

• G06F30/367

  Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods · CPC title