Data transfer using a descriptor

Patent metadata

Field	Value
Publication number	US-9916268-B2
Application number	US-201414551798-A
Country	US
Kind code	B2
Filing date	Nov 24, 2014
Priority date	Nov 29, 2013
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A data processing apparatus includes a number of processor cores, a shared processor cache, a bus unit and a bus controller. The shared processor cache is connected to each of the processor cores and to a main memory. The bus unit is connected to the shared processor cache by a bus controller for transferring data to/from an I/O device. In order to achieve further improvements to the data transfer rate between the processor cache and I/O devices, the bus controller is configured, in response to receiving a descriptor from a processor core, to perform a direct memory access to the shared processor cache for transferring data according to the descriptor from the shared processor cache to the I/O device via the bus unit.

First claim

What is claimed is:

1. A method of operating a data processing apparatus in connection with an I/O device, the method comprising:
receiving by a bus controller of the data processing apparatus a descriptor sent to said bus controller by a processor core of the data processing apparatus;
transferring by the bus controller, operating according to said descriptor, data from a shared processor cache coupled to said bus controller to said I/O device
writing the descriptor to the shared processor cache by the processor core; and
forwarding the descriptor to the bus controller by the shared processor cache.

2. The method according to claim 1 , further comprising creating the descriptor by the processor core.

3. The method according to claim 1 , further comprising based on receiving the descriptor, driven by the bus controller, the said shared processor cache to fetch the data from a main memory coupled to the shared processor cache.

4. The method according to claim 1 , wherein said shared processor cache comprises multiple integral cache devices connected together in a network, each of said integral cache devices being connected to one or more processor cores.

5. The method according to claim 1 , wherein said shared processor cache is part of a multi-level cache hierarchy.

6. The method of claim 1 , wherein the data processing apparatus comprises a processor, the processor comprising the processor core, the shared processor cache, and the bus controller.

7. A computer program product comprising:
a computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising:
receiving by a bus controller of a data processing apparatus a descriptor sent to said bus controller by a processor core of the data processing apparatus;
transferring by the bus controller, operating according to said descriptor, data from a shared processor cache coupled to said bus controller to an I/O device;
writing the descriptor to the shared processor cache by the processor core; and
forwarding the descriptor to the bus controller by the shared processor cache.

8. The computer program product according to claim 7 , wherein the method further comprises creating the descriptor by the processor core.

9. The computer program product according to claim 7 , wherein the method further comprises based on receiving the descriptor, driven by the bus controller, the said shared processor cache to fetch the data from a main memory coupled to the shared processor cache.

Assignees

• IBM

Inventors

• Hagspiel Norbert
• Junghans Sascha
• Klein Matthias
• Walter Joerg

Classifications

• G06F12/0868

  Data transfer between cache memory and other subsystems, e.g. storage devices or host systems · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F13/28 Primary

  using burst mode transfer, e.g. direct memory access {DMA}, cycle steal (G06F13/32 takes precedence) · CPC title

• G06F12/084

  with a shared cache · CPC title

• G06F12/0871

  Allocation or management of cache space · CPC title