Method and apparatus for TLB shoot-down in a heterogeneous computing system supporting shared virtual memory

Patent metadata

Field	Value
Publication number	US-9916257-B2
Application number	US-201113191327-A
Country	US
Kind code	B2
Filing date	Jul 26, 2011
Priority date	Jul 26, 2011
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Methods and apparatus are disclosed for efficient TLB (translation look-aside buffer) shoot-downs for heterogeneous devices sharing virtual memory in a multi-core system. Embodiments of an apparatus for efficient TLB shoot-downs may include a TLB to store virtual address translation entries, and a memory management unit, coupled with the TLB, to maintain PASID (process address space identifier) state entries corresponding to the virtual address translation entries. The PASID state entries may include an active reference state and a lazy-invalidation state. The memory management unit may perform atomic modification of PASID state entries responsive to receiving PASID state update requests from devices in the multi-core system and read the lazy-invalidation state of the PASID state entries. The memory management unit may send PASID state update responses to the devices to synchronize TLB entries prior to activation responsive to the respective lazy-invalidation state.

First claim

What is claimed is:

1. An apparatus comprising:
a TLB to store a plurality of virtual address translation entries; and
a memory management unit, coupled with the TLB, to maintain PASID state entries corresponding to a portion of the virtual address translation entries, each of said PASID state entries including an active reference count and a lazy-invalidation field,
said memory management unit to perform an atomic modification of a first PASID state entry responsive to receiving a first PASID state update request from a device of a plurality of heterogeneous devices in a multi-core system and to read the lazy-invalidation state of the first PASID state entry,
the memory management unit to send a PASID state update response to the device to synchronize a device TLB entry prior to activation responsive at least in part to the lazy-invalidation state read.

2. The apparatus of claim 1 wherein the atomic modification of the first PASID state comprises:
reading the first PASID state entry including the lazy-invalidate state;
incrementing an active reference count if the first PASID state update request indicates an activation update; and
clearing the lazy-invalidate state if the first PASID state update request indicates an activation update.

3. The apparatus of claim 1 wherein the memory management unit responsive at least in part to the lazy-invalidation state read is further to:
invalidate a TLB virtual address translation entry corresponding to the first PASID state entry; and
set a synchronization flag for the PASID state update response sent to the device.

4. The apparatus of claim 1 wherein the memory management unit is further to:
process a TLB shoot-down from an operating system in the multi-core system.

5. The apparatus of claim 4 wherein processing a TLB shoot-down comprises:
invalidating a TLB virtual address translation entry.

6. The apparatus of claim 4 wherein processing a TLB shoot-down comprises:
causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated.

7. The apparatus of claim 4 wherein processing a TLB shoot-down comprises:
reading a PASID state entry; and
setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

8. The apparatus of claim 7 wherein processing a TLB shoot-down comprises:
invalidating a TLB entry if the active reference count in the PASID state entry is not zero; and
causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated if the active reference count in the PASID state entry is not zero.

9. The apparatus of claim 7 wherein setting a lazy-invalidate field in the PASID state entry is performed using a locked compare-and-exchange instruction.

10. A multi-core processor comprising:
a first plurality of homogeneous processing cores;
a heterogeneous processing device;
a TLB to store a plurality of virtual address translation entries; and
a memory management unit, coupled with the TLB, to maintain PASID state entries corresponding to a portion of the virtual address translation entries, each of said PASID state entries including an active reference count and a lazy-invalidation field,
said memory management unit to perform an atomic modification of a first PASID state entry responsive to receiving a first PASID state update request from a device of a plurality of heterogeneous devices in the multi-core processor and to read the lazy-invalidation state of the first PASID state entry,
the memory management unit to send a PASID state update response to the device to synchronize a device TLB entry prior to activation responsive at least in part to the lazy-invalidation state read.

11. The multi-core processor of claim 10 wherein the atomic modification of the first PASID state entry comprises:
reading the first PASID state entry including the lazy-invalidate state;
incrementing an active reference count if the first PASID state update request indicates an activation update; and
clearing the lazy-invalidate state if the first PASID state update request indicates an activation update.

12. The multi-core processor of claim 10 wherein the memory management unit is further to process a TLB shoot-down from an operating system.

13. The multi-core processor of claim 12 wherein processing a TLB shoot-down comprises:
reading a PASID state entry; and
setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

14. The multi-core processor of claim 13 wherein processing a TLB shoot-down comprises:
invalidating a TLB entry if the active reference count in the PASID state entry is not zero; and
causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated if the active reference count in the PASID state entry is not zero.

15. The multi-core processor of claim 13 wherein setting a lazy-invalidate field in the PASID state entry is performed using a locked compare-and-exchange instruction.

16. A multi-core system comprising:
a memory to store a plurality of page tables containing virtual address translation entries;
a first plurality of homogeneous processing cores;
a heterogeneous processing device;
a TLB to store a plurality of the virtual address translation entries; and
a memory management unit, coupled with the TLB, to maintain PASID state entries corresponding to a portion of the virtual address translation entries, each of said PASID state entries including an active reference count and a lazy-invalidation field,
said memory management unit to perform an atomic modification of a first PASID state entry responsive to receiving a first PASID state update request from a device of a plurality of heterogeneous devices in the multi-core system and to read the lazy-invalidation state of the first PASID state entry,
the memory management unit to send a PASID state update response to the device to synchronize a device TLB entry prior to activation responsive at least in part to the lazy-invalidation state read.

17. The multi-core system of claim 16 wherein the memory management unit is further to:
process a TLB shoot-down from an operating system in the multi-core system.

18. The multi-core system of claim 17 wherein processing a TLB shoot-down comprises:
causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated.

19. The multi-core system of claim 17 wherein processing a TLB shoot-down comprises:
reading a PASID state entry; and
setting a lazy-invalidate field in the PASID state entry if an active reference count in the PASID state entry is zero.

20. The multi-core system of claim 19 wherein processing a TLB shoot-down comprises:
invalidating a TLB entry if the active reference count in the PASID state entry is not zero; and
causing a device TLB entry of one of the plurality of heterogeneous devices to be invalidated if the active reference count in the PASID state entry is not zero.

Assignees

• Sankaran Rajesh M
• Koker Altug
• Lantz Philip R
• Mallick Asit K
• Crossland James B
• Navale Aditya
• Neiger Gilbert
• Anderson Andrew V
• Intel Corp

Inventors

• Sankaran Rajesh M
• Koker Altug
• Lantz Philip R
• Mallick Asit K
• Crossland James B
• Navale Aditya
• Neiger Gilbert
• Anderson Andrew V

Classifications

• G06F12/1027 Primary

  using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB] · CPC title

• G06F2212/683

  Invalidation · CPC title

• G06F2212/682

  Multiprocessor TLB consistency · CPC title

• G06F2212/303

  In peripheral interface, e.g. I/O adapter or channel · CPC title

• G06F2212/1048

  Scalability · CPC title