Techniques for maintaining cache coherence by atomically processing groups of storage commands

Patent metadata

Field	Value
Publication number	US-9916244-B1
Application number	US-201615282209-A
Country	US
Kind code	B1
Filing date	Sep 30, 2016
Priority date	Sep 30, 2016
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

Improved techniques for maintaining cache coherence in a consistent state are provided. These techniques implement a data storage system using a journaled mirrored cache that ensures that storage operations making up certain transactions be performed atomically, so that a system failure does not result in data loss. The improved techniques also allow for efficient communication of mirroring information.

First claim

What is claimed is:

1. A method, performed by a data storage system (DSS), of maintaining cache coherence in a consistent state, the method comprising:
by a mapping driver running on a set of processing circuitry of the DSS, identifying a plurality of related storage operations that must be performed atomically to avoid incoherency within a log-based cache of the set of processing circuitry, the log-based cache of the set of processing circuitry being maintained by a mirrored cache driver (MCD) running on the set of processing circuitry;
in response to identifying the plurality of related data storage commands, generating, by the mapping driver, an inter-driver communication structure (IDCS), the IDCS including instructions to perform the plurality of storage commands in parallel;
sending the generated IDCS from the mapping driver to the MCD running on the set of processing circuitry;
in response to the MCD receiving the IDCS from the mapping driver, provisionally executing, by the MCD, each of the plurality of storage commands as directed by the ICDS, resulting in a set of provisional changes to the log-based cache of the set of processing circuitry as maintained by the MCD; and
in response to successfully completing provisionally executing all of the plurality of storage commands, committing, by the MCD, the set of provisional changes to the log- based cache of the set of processing circuitry.

2. The method of claim 1 ,
wherein the method further comprises, in response to successfully completing provisionally executing all of the plurality of storage commands and prior to committing the set of provisional changes, sending, over an inter-processor bus, a description of the set of changes from the MCD to a peer MCD running on another set of processing circuitry of the DSS, the peer MCD maintaining a peer version of the log-based cache on the other set of processing circuitry; and
wherein committing the set of provisional changes to the log-based cache of the set of processing circuitry is further performed in response to receiving, by the MCD, confirmation that one of (a) the peer MCD has successfully updated the peer version of the log-based cache by the peer MCD having implemented the set of changes on the peer version of the log-based cache and (b) the peer MCD has gone offline.

3. The method of claim 2 wherein:
provisionally executing each of the plurality of storage commands as directed by the ICDS includes marking, by the MCD, a cache page within the log-based cache of the set of processing circuitry as being in a prepared state; and
committing the set of provisional changes to the log-based cache of the set of processing circuitry includes marking, by the MCD, the cache page within the log-based cache of the set of processing circuitry as being in one of a valid state and a dirty state.

4. The method of claim 3 wherein the peer MCD is configured to, while implementing the set of changes on the peer version of the log-based cache, mark another cache page within the peer version of the log-based cache as being in one of the valid state and the dirty state.

5. The method of claim 1 wherein the plurality of related storage operations that must be performed atomically to avoid incoherency within the log-based cache include:
a write command directed to a block of the log-based cache, the block of the log-based cache being backed by a cache page maintained by the MCD, the write command including data received from a remote host device performing a write to a destination address on the logical disk of the DSS; and
a copy command directed to a datalog descriptor of the log-based cache, the datalog descriptor of the log-based cache being backed by another cache page maintained by the MCD, the datalog descriptor indicating the destination address and indicating a location of the cache page.

6. The method of claim 1 wherein the plurality of related storage operations that must be performed atomically to avoid incoherency within the log-based cache include:
a cache rename command to cause a cache page maintained by the MCD that was backing a block of the log-based cache to instead back a block on a logical disk of the DSS; and
an invalidation command to cause a datalog descriptor of the log-based cache to become invalidated, the datalog descriptor pointing to the block of the log-based cache that was backed by the cache page maintained by the MCD.

7. The method of claim 1 wherein the IDCS includes an atomic section, the atomic section including the plurality of storage commands.

8. The method of claim 7 wherein the atomic section is configured to store up to 128 storage commands.

9. The method of claim 7 wherein the IDCS further includes another atomic section, the other atomic section including another plurality of storage commands that must be performed atomically by the MCD.

10. The method of claim 1 wherein the IDCS includes a reference to a set of buffers containing the plurality of storage commands, the plurality of storage commands making up an atomic section.

11. The method of claim 10 wherein the atomic section is configured to include up to 128 storage commands.

12. The method of claim 10 wherein the set of buffers further includes another atomic section, the other atomic section including another plurality of storage commands that must be performed atomically by the MCD.

13. A data storage system (DSS) apparatus comprising:
a set of persistent storage devices;
a set of processing circuitry including processors coupled to memory, the processing circuitry being configured to:
by a mapping driver running on the set of processing circuitry, identify a plurality of related storage operations that must be performed atomically to avoid incoherency within a log-based cache of the set of processing circuitry, the log-based cache of the set of processing circuitry being maintained by a mirrored cache driver (MCD) running on the set of processing circuitry, the plurality of related storage operations being directed to storage constructs backed by the set of persistent storage devices;
in response to identifying the plurality of related data storage commands, generate, by the mapping driver, an inter-driver communication structure (IDCS), the IDCS including instructions to perform the plurality of storage commands in parallel;
send the generated IDCS from the mapping driver to the MCD running on the set of processing circuitry;
in response to the MCD receiving the IDCS from the mapping driver, provisionally execute, by the MCD, each of the plurality of storage commands as directed by the ICDS, resulting in a set of provisional changes to the log-based cache of the set of processing circuitry as maintained by the MCD; and
in response to successfully completing provisionally executing all of the plurality of storage commands, commit, by the MCD, the set of provisional changes to the log-based cache of the set of processing circuitry.

14. A computer program product comprising a non-transitory computer-readable storage medium storing a set of instructions, which, when executed by a data storage system device, cause the DSS device to:
execute a mapping driver on a set of processing circuitry of the DSS device in order to:
identify a plurality of related storage operations that must be performed atomically to avoid incoherency within a log-based cache of the set of processing circuitry, the log-based cache of the set of processing circuitry being maintained by a mirrored cache driver (MCD) running on the set of processing circuitry;
in response to identifying the plurality of related data storage commands, generate an int

Assignees

• Emc Ip Holding Co Llc

Inventors

• Tolvanen Peter E
• Spang Iv Henry Austin
• Schaffer Gregory S
• Armangau Philippe
• Seibel Christopher A

Classifications

• G06F3/065

  Replication mechanisms · CPC title

• G06F12/0808 Primary

  with cache invalidating means (G06F12/0815 takes precedence) · CPC title

• G06F12/128

  adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel · CPC title

• G06F3/0619

  in relation to data integrity, e.g. data losses, bit errors · CPC title

• G06F2212/621

  Coherency control relating to peripheral accessing, e.g. from DMA or I/O device · CPC title