Multi-stacked electronic device with defect-free solder connection

Patent metadata

Field	Value
Publication number	US-9913375-B2
Application number	US-201615276073-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	Jul 16, 2014
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.

First claim

What is claimed is:

1. An electronic structure comprising:
a substrate having an upper soldering surface;
a stacked electronic device having at least first and second electronic components, the first electronic component including a lateral, outside downwardly extending first leadframe, the second electronic component including a lateral, upwardly extending leadframe, the second leadframe extending upwardly, laterally inside of, and vertically overlapping with, the first leadframe, wherein the first and second leadframes include respective overlapping portions, and the first leadframe includes a lower portion spaced from said overlapping portions and defining a solder connection region for soldering the stacked electronic device to a soldering surface;
a joint located outside the solder connection region, and directly between and physically joining together the overlapping portions of the first and second leadframes to join the first and second electronic components together; and
a solder connection below and spaced from the joint and joining the solder connection region of the stacked electronic device to the soldering surface, the solder connection including a solder material having a melting point lower than a melting point of the joint.

2. The electronic structure according to claim 1 , wherein the solder material of the solder connection includes a lead free solder.

3. The electronic structure according to claim 1 , wherein the substrate includes an epoxy dielectric material.

4. The electronic structure according to claim 1 , wherein the substrate includes an epoxy dielectric material with a metal foil on an upper surface of the epoxy dielectric material.

5. The electronic structure according to claim 1 , wherein the solder connection extends laterally outside the stacked electronic device.

6. The electronic structure according to claim 1 , wherein the solder connection extends laterally outside the overlapping portions of the first and second leadframes.

7. The electronic structure according to claim 1 , wherein the solder connection is below the joint.

8. The electronic structure according to claim 1 , wherein the solder connection extends laterally outside the second electronic component.

9. The electronic structure according to claim 1 , wherein the solder connection is beneath the leadframes of the second electronic component.

10. The electronic structure according to claim 1 , wherein the solder connection extends laterally inward of the first and second leadframes.

Assignees

• IBM

Inventors

• Ang Ai Kiar
• Lauri Michael

Classifications

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W70/40

  Leadframes · CPC title

• H10W90/811

  Multiple chips on leadframes · CPC title

• H10W90/00

  Package configurations · CPC title

• H10W70/442

  of multiple leadframes in a single chip · CPC title