Reception apparatus and system

Patent metadata

Field	Value
Publication number	US-9912427-B2
Application number	US-201615196179-A
Country	US
Kind code	B2
Filing date	Jun 29, 2016
Priority date	Jul 17, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A reception apparatus for receiving data from a transmission apparatus includes a data receiver configured to receive a synchronization packet including clock information generated by the transmission apparatus and data from the transmission apparatus, a storage memory, storing the received data, a clock adjuster configured to correct a clock of the reception apparatus based on a deviation between a clock of the transmission apparatus and the clock of the reception apparatus by using the clock information generated by the transmission apparatus, a controller configured to control a clock correction amount of the clock adjuster based on a storage amount of data in the storage memory, and a data output circuit configured to retrieve the data from the storage memory to output the retrieved data in synchronization with the corrected clock.

First claim

What is claimed is:

1. A reception apparatus for receiving data from a transmission apparatus, comprising:
a data receiver configured to receive a synchronization packet including clock information generated by the transmission apparatus and data from the transmission apparatus;
a storage memory, storing the received data;
a clock adjuster configured to correct a clock of the reception apparatus based on a deviation between a clock of the transmission apparatus and the clock of the reception apparatus by using the clock information generated by the transmission apparatus;
a controller configured to control a clock correction amount of the clock adjuster based on a storage amount of data in the storage memory; and
a data output circuit configured to retrieve the data from the storage memory to output the retrieved data in synchronization with the corrected clock,
wherein the controller controls the clock correction amount of the clock adjuster so that at least an amount of data is stored in the storage memory, the amount corresponding to a maximum value of the deviation,
wherein the amount is defined as N×M wherein N indicates a pixel clock frequency and M indicates the maximum value of the deviation, and
wherein the maximum value of the deviation is defined as P×Q, wherein P indicates a clock synchronous precision and Q indicates an interval between transmissions of the synchronization packets.

2. The reception apparatus according to claim 1 , wherein a storage capacity of the storage memory is twice or more of the amount corresponding to the maximum value of the deviation.

3. The reception apparatus according to claim 1 , wherein the deviation is calculated by the clock adjuster based on a counted number of clocks in the transmission apparatus during a transmission interval of the synchronization packet and a counted number of clocks in the reception apparatus during a reception interval of the synchronization packet.

4. The reception apparatus according to claim 1 , wherein the controller controls the clock correction amount of clock adjuster so that an amount of data is stored in the storage memory, the amount corresponding to a minimum unit of encoded data required for decoding the encoded data.

5. A system including a transmission apparatus, a reception apparatus for receiving data from the transmission apparatus, and a synchronization apparatus for transmitting synchronization packets to the transmission apparatus and the reception apparatus, wherein respective synchronization packets transmitted from the synchronization apparatus to the transmission apparatus and to the reception apparatus include the same clock information,
the transmission apparatus comprising:
a first clock adjuster configured to correct a clock of the transmission apparatus based on a deviation between a clock of the synchronization apparatus and a clock of the transmission apparatus by using the clock information included in the received synchronization packet;
the reception apparatus comprising:
a data receiver configured to receive the synchronization packet transmitted from the synchronization apparatus and data transmitted from the transmission apparatus;
a storage memory, storing the received data in a storage memory;
a second clock adjuster configured to correct a clock of the reception apparatus based on a deviation between a clock of the synchronization apparatus and the clock of the reception apparatus by using the clock information included in the received synchronization packet;
a controller configured to control a clock correction amount of the clock adjuster based on a storage amount of data in the storage memory; and
a data output circuit configured to retrieve the data from the storage memory to output the retrieved data to an external apparatus in synchronization with the corrected clock,
wherein the controller controls the clock correction amount of the clock adjuster so that at least an amount of data is stored in the storage memory, the amount corresponding to a maximum value of the deviation,
wherein the amount is defined as N×M wherein N indicates a pixel clock frequency and M indicates the maximum value of the deviation, and
wherein the maximum value of the deviation is defined as P×Q, wherein P indicates a clock synchronous precision and Q indicates an interval between transmissions of the synchronization packets.

Assignees

• Sadasue Tamon
• Kajiwara Yasuhiro
• Takazawa Kazuhiro
• Matsushita Kazufumi
• Shirataka Yasuko
• Hashimoto yasuko
• Aoki Satoshi
• Ricoh Co Ltd

Inventors

• Sadasue Tamon
• Kajiwara Yasuhiro
• Takazawa Kazuhiro
• Matsushita Kazufumi
• Shirataka Yasuko
• Hashimoto yasuko
• Aoki Satoshi

Classifications

• H04J3/0658 Primary

  Clock or time synchronisation among packet nodes · CPC title

• H04N21/4305

  Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets (arrangements for synchronising receiver with transmitter by comparing receiver clock with transmitter clock H04L7/0012; arrangements for synchronising receiver with transmitter wherein the receiver takes measures against momentary loss of synchronisation H04L7/0083) · CPC title

• H04N21/242

  Synchronisation processes, e.g. processing of PCR [Programme Clock References] {(arrangements for synchronising broadcast or distribution via plural systems in broadcast distribution systems H04H20/18)} · CPC title

• H04L65/80

  Responding to QoS · CPC title

• H04L12/40078

  Bus configuration (home automation networks H04L12/2803; arrangements for maintenance or administration H04L41/00) · CPC title