Digital polar transmitter having a digital front end

Patent metadata

Field	Value
Publication number	US-9912357-B1
Application number	US-201615382808-A
Country	US
Kind code	B1
Filing date	Dec 19, 2016
Priority date	Dec 19, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A digital polar transmitter arrangement having a digital front end (DFE) and a transmit chain is disclosed. The DFE is configured to resample a baseband signal relative to a carrier frequency at a carrier frequency related sample rate, calculate zero crossing positions of the resampled signal, generate delay to time converter (DTC) commands based on the zero crossing positions, calculate amplitude values for the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the amplitude values. The transmit chain is configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.

First claim

What is claimed is:

1. A digital polar transmitter arrangement comprising:
a digital front end (DFE) configured to resample a baseband signal at a frequency related to a carrier frequency,
calculate zero crossing positions of the resampled signal,
generate delay to time converter (DTC) commands based on the zero crossing positions,
calculate amplitude values for the zero crossing positions, and
generate dynamic phase alignment (DPA) commands based on the amplitude values; and

a transmit chain configured to generate an output signal having amplitude and polar modulation for transmission based on the DPA commands and the DTC commands.

2. The arrangement of claim 1 , wherein the DFE comprises a variable rate converter (VRC) configured to resample the baseband signal.

3. The arrangement of claim 1 , wherein the DFE comprises a low power interpolator configured to resample the baseband signal at the carrier frequency related sample rate.

4. The arrangement of claim 1 , wherein the DFE comprises a zero crossing finder configured to determine the zero crossing positions.

5. The arrangement of claim 1 , wherein the DFE comprises a zero crossings correction component configured to apply corrections to rising and falling edges of the resampled signal.

6. The arrangement of claim 1 , wherein the DFE comprises a power amplifier configured to calculate the amplitude values for the zero crossing positions.

7. The arrangement of claim 1 , where the transmit chain comprises a DTC component configured to generate a modulated clock having phase modulation based on the DTC commands and a voltage controlled oscillator signal.

8. The arrangement of claim 1 , wherein the transmit chain comprises a DPA component configured to generate the output signal having amplitude modulation based on the DPA commands and a modulated clock signal.

9. The arrangement of claim 1 , wherein the transmit chain comprises a band pass filter configured to remove noise and unwanted signals from the output signal.

10. The arrangement of claim 1 , wherein the baseband signal is a digital Cartesian signal having inphase (I) and quadrature (Q) components.

11. A digital front end (DFE) arrangement comprising:
a variable rate converter (VRC) configured to resample a baseband signal;
a low power interpolator (LPI) configured to interpolate the resampled signal based on a carrier frequency;
a zero crossing finder configured to calculate zero crossing positions based on the interpolated signal;
a converter configured to convert the zero crossing positions into delay to time (DTC) commands; and
an amplifier configured to calculate amplitude values of the interpolated signal at the zero crossing positions and generate dynamic phase alignment (DPA) commands based on the calculated amplitude values.

12. The arrangement of claim 11 , further comprising a modem configured to generate the baseband signal as a Cartesian signal having in-phase (I) and quadrature (Q) components.

13. The arrangement of claim 11 , wherein the VRC and the LPI operate on a carrier frequency related signal.

14. The arrangement of claim 11 , wherein the converter operates at a modulated clock.

15. The arrangement of claim 11 , wherein the converter converts the zero crossing positions using a zero crossing delay and a voltage controlled oscillator clock.

16. The arrangement of claim 11 , further comprising a correction component configured to calculate an edge error based on a signal having the zero crossing positions and apply a compensation based on the calculated edge error to edges of the signal and provide the signal having the applied compensation to the converter.

17. The arrangement of claim 11 , further comprising a transmit chain configured to generate an output signal having amplitude and phase modulation based on the DTC and DPA commands.

18. A method of operating a digital transmitter comprising:
generating a digital baseband signal having inphase (I) and quadrature (Q) components;
resampling the baseband signal at a frequency related to a carrier frequency and higher than a baseband frequency of the baseband signal;
calculating zero crossing positions based on the resampled baseband signal having I and Q components; and
converting the zero crossing positions into delay to time (DTC) commands.

19. The method of claim 18 , further comprising calculating amplitudes values of the resampled baseband signal at the zero crossing positions to generate DPA commands.

20. The method of claim 18 , further comprising interpolating the resampled baseband signal prior to calculating the zero crossing positions.

21. The method of claim 18 , further comprising generating an output signal having amplitude and phase modulation based on the DTC and DPA commands.

Assignees

• Intel Ip Corp

Inventors

• Parker Uri
• Banin Elan
• Kerner Michael
• Degani Ofir

Classifications

• H04B1/02 Primary

  Transmitters · CPC title

• H02M1/12

  Arrangements for reducing harmonics from AC input or output · CPC title

• G11B20/10055

  using partial response filtering when writing the signal to the medium or reading it therefrom · CPC title

• G11B20/1024

  wherein a phase-locked loop [PLL] is used · CPC title

• H02P27/08

  with pulse width modulation · CPC title