Flash analog-to-digital converter calibration

Patent metadata

Field	Value
Publication number	US-9912342-B2
Application number	US-201615369175-A
Country	US
Kind code	B2
Filing date	Dec 5, 2016
Priority date	Dec 18, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

An analog-to-digital converter (ADC) is a device that can include a reference shuffler and a loop filter. An ADC can achieve better performance with incremental adjustment of a pointer of the reference shuffler, changing coefficients of the loop filter, and storing calibration codes of the ADC in a non-volatile memory. By incrementally adjusting a pointer of the reference shuffler, a calibration can be performed more efficiently than with a random adjustment of the pointer. By temporarily changing the loop filter coefficients, a greater amount of activity can be introduced into the loop filter. This activity can allow the calibration to proceed more efficiently. By storing the calibration codes in a non-volatile memory, a search space for calibration codes can be reduced. Thus, a calibration can occur more quickly, and the calibration itself can be improved.

First claim

The invention claimed is:

1. A system for calibrating an analog-to-digital converter, the system comprising:
the analog-to-digital converter, which receives an analog input and includes a comparator that compares the analog input to a reference voltage, and a reference shuffler that shuffles a reference for the reference voltage of the comparator, the comparator to convert the analog input to digital data based on the reference;
an RMS meter that measures a power of the digital data;
calibration logic that calibrates the analog-to-digital converter based on the power of the digital data; and
a nonvolatile memory that stores a calibration code for the analog-to-digital converter, wherein the calibration logic changes the calibration code by a first predetermined value to produce a changed calibration code, the analog-to-digital converter produces an output based on the changed calibration code, and the calibration logic stores the changed calibration code in the nonvolatile memory, if the output is less than a second predetermined value.

2. The system of claim 1 , wherein the calibration logic retrieves the calibration code from the nonvolatile memory.

3. The system of claim 1 , wherein the calibration logic determines whether the power of the digital data is less than a predetermined value.

4. The system of claim 1 , wherein the calibration logic determines a calibration code that minimizes a power output for the analog-to-digital converter.

5. The system of claim 1 , wherein the calibration logic changes the calibration code by decreasing the calibration code by the first predetermined value to produce the changed calibration code.

6. The system of claim 1 , wherein the calibration logic changes the calibration code by increasing the calibration code by the first predetermined value to produce the changed calibration code.

7. A system for a calibration of an analog-to-digital converter, the system comprising:
a plurality of comparators that receive an input analog signal, compare the input analog signal to a plurality of references, and output a digital signal;
a reference shuffler that shuffles the plurality of references;
an RMS meter that receives the digital signal and outputs a measured signal; and
calibration logic configured to perform an incremental shuffling for the plurality of comparators and to determine a calibration coefficient that minimizes an average flash power of one of the plurality of comparators, based on the measured signal, wherein the calibration logic computes a total flash power for each of the references and divides the total flash power by a number of shuffler references to determine the average flash power.

8. The system of claim 7 , wherein the calibration coefficient is determined for a plurality of calibration coefficient values.

9. The system of claim 7 , wherein the calibration logic calibrates each of the plurality of comparators.

10. The system of claim 7 , wherein the calibration is performed a predetermined number of times.

11. The system of claim 7 , wherein the calibration logic is configured to randomly change the calibration coefficient to produce a seed for a next calibration.

12. A non-transitory, computer readable storage medium encoded with computer program instructions, executable by a processor, for performing operations for calibrating an analog-to-digital converter, the operations comprising:
plotting a transfer function for the analog-to-digital converter in a frequency domain;
determining whether an infinity norm of the transfer function is sufficient;
determining whether the analog-to-digital converter is stable;
converting the transfer function of the analog-to-digital converter to a value of a component of the analog-to-digital converter, wherein the component is a resistor, capacitor, or current source;
simulating a calibration of the analog-to-digital converter; and
writing the value of the component to the analog-to-digital converter, if the analog-to-digital converter is determined to be stable.

13. The medium of claim 12 , the operations further comprising:
moving transfer function poles away from a z-domain unit circle, if the infinity norm of a filter of the analog-to-digital converter exceeds a threshold.

14. The medium of claim 13 , the operations further comprising:
moving transfer function poles closer to the z-domain unit circle, if the infinity norm of the filter does not exceed the threshold.

15. A non-transitory, computer readable storage medium encoded with computer program instructions, executable by a processor, for performing operations for calibrating an analog-to-digital converter, the operations comprising:
calibrating the analog-to-digital converter based on a power of digital data measured by an RMS meter;
changing a calibration code, stored by a nonvolatile memory, by a first predetermined value to produce a changed calibration code, wherein the analog-to-digital converter compares an analog input to a reference voltage, converts the analog input to the digital data based on a reference for the reference voltage, and produces an output based on the changed calibration code; and
storing the changed calibration code in the nonvolatile memory, if the output is less than a second predetermined value.

16. The medium of claim 15 , the operations further comprising:
determining a calibration code that minimizes a power output for the analog-to-digital converter.

17. A non-transitory, computer readable storage medium encoded with computer program instructions, executable by a processor, for a calibration of an analog-to- digital converter, the operations comprising:
performing an incremental shuffling for a plurality of comparators, wherein the plurality of comparators compare an analog signal to a plurality of references and output a digital signal, and the plurality of references are shuffled by a reference shuffler;
determining a calibration coefficient that minimizes an average flash power of one of the plurality of comparators, based on a measured signal output by an RMS meter that receives the digital signal;
computing a total flash power for each of the references; and
dividing the total flash power by a number of shuffler references to determine the average flash power.

18. The medium of claim 17 , the operations further comprising:
randomly changing the calibration coefficient to produce a seed for a next calibration.

19. An apparatus for calibrating an analog-to-digital converter, comprising:
a memory that stores instructions; and
a processor configured to execute the instructions to plot a transfer function for the analog-to-digital converter in a frequency domain, to determine whether an infinity norm of the transfer function is sufficient, to determine whether the analog-to-digital converter is stable, to convert the transfer function of the analog-to-digital converter to a value of a component of the analog-to-digital converter, wherein the component is a resistor, capacitor, or current source, to simulate a calibration of the analog-to-digital converter, and to write the value of the component to the analog-to-digital converter, if the analog-to-digital converter is determined to be stable.

20. The apparatus of claim 19 , wherein the processor moves transfer function poles away from a z-domain unit circle, if the infinity norm of a filter of the analog-to-digital converter exceeds a threshold.

Assignees

• Analog Devices Global

Inventors

• Li Zhao
• Shibata Hajime
• Caldwell Trevor Clifford
• Dong Yunzhi
• Zhao Jialin
• Schreier Richard E
• Kozlov Victor
• Alldred David Nelson
• Shrestha Prawal Man

Classifications

• H03M1/34

  Analogue value compared with reference values (H03M1/48 takes precedence) · CPC title

• H03M3/422

  having one quantiser only · CPC title

• H03M1/1009 Primary

  Calibration · CPC title

• H03M1/0626

  by filtering · CPC title

• H03M3/388 Primary

  by storing corrected or correction values in one or more digital look-up tables · CPC title