Data conversion with redundant split-capacitor arrangement

Patent metadata

Field	Value
Publication number	US-9912341-B2
Application number	US-201313783054-A
Country	US
Kind code	B2
Filing date	Mar 1, 2013
Priority date	Mar 1, 2013
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant split-capacitor arrangement using a successive approximation technique can provide a fast and power efficient ADC. For example, a successive approximation capacitor arrangement may include multiple arrays with non-binary bit weights.

First claim

What is claimed is:

1. An apparatus, comprising:
a first array of capacitances coupled to a common node, each successive capacitance of the first array having a capacitance value that is less than a capacitance value of a previous adjacent capacitance, according to a predetermined non-binary numerical pattern; and
a second array of capacitances coupled to the common node, each capacitance of the first array having an associated capacitance within the second array with an approximately equivalent capacitance value, the first array and the second array in combination arranged to determine a digital approximation for an analog input value,
wherein the voltage at the common node is based on one or more capacitors of the first array being coupled to a reference voltage or to the ground potential and the voltage at the other common node is based on one or more capacitors of the second array being coupled to the reference voltage or to the ground potential, the one or more capacitors of the first array and/or the one or more capacitors of the second array being coupled to the reference voltage or to the ground potential in pairs, each pair comprising a capacitor of the first array and an associated capacitor of the second array, according to a search algorithm.

2. The apparatus of claim 1 , further comprising a comparator arranged to compare a voltage at the common node to a ground potential, the digital approximation based on the comparison.

3. The apparatus of claim 2 , wherein the voltage at the common node is based on one or more capacitances of the first array and/or one or more capacitances of the second array being coupled to a reference voltage or to the ground potential, after the first array and the second array in combination has been charged to the analog input value.

4. The apparatus of claim 3 , wherein the one or more capacitances of the first array and/or one or more capacitances of the second array are coupled to the reference voltage or to the ground potential in pairs, each pair comprising a capacitance of the first array and an associated capacitance of the second array.

5. The apparatus of claim 3 , wherein the one or more capacitances of the first array and/or one or more capacitances of the second array are coupled to the reference voltage or to the ground potential according to a successive approximation binary search algorithm.

6. The apparatus of claim 1 , the first array and the second array each further comprising an additional capacitance having a capacitance value approximately equivalent to at least one other of the capacitances of the first and second arrays.

7. The apparatus of claim 1 , wherein the predetermined non-binary numerical pattern is a scale or a ratio.

8. The apparatus of claim 1 , wherein the predetermined non-binary numerical pattern is a numerical sequence.

9. The apparatus of claim 1 , wherein each of the capacitances of the first array and the second array are assigned a bit weight based on a position of the capacitance within the respective array and according to the predetermined non-binary numerical pattern, a sum of multiple consecutive bit weights being greater than a value of a next higher position bit weight.

10. The apparatus of claim 9 , wherein the sum of the multiple consecutive bit weights need not be greater than a value of a next higher position bit weight when the next higher position bit weight has a bit position lower than a predetermined bit position.

11. The apparatus of claim 1 , wherein one or more capacitances of the first array and/or the second array are comprised of multiple capacitive elements.

12. The apparatus of claim 1 , wherein a pair of capacitances including a capacitance of the first array and an associated capacitance of the second array is assigned a bit weight based on a position of the pair of capacitances within the arrays and according to the predetermined non-binary numerical pattern, the digital approximation for the analog input value based on a sum of bit weights of pairs of capacitances coupled to a reference voltage.

13. An analog-to-digital converter (ADC), comprising:
a successive approximation (SA) capacitor array arranged to determine a digital approximation of an analog input voltage, the SA capacitor array including:
a first array of capacitors, each successive capacitor of the first array having a capacitance value that is less than a capacitance value of a previous adjacent capacitor, according to a predetermined non-binary numerical pattern, and
a second array of capacitors, each capacitor of the first array having an associated capacitor within the second array with an approximately equivalent capacitance value, the first array and the second array in combination arranged to determine the digital approximation for the analog input value;
a digital-to-analog converter (DAC) arranged to determine an analog value of the digital approximation; and
a first comparator arranged to compare the analog input voltage to the output of the DAC, and to output a comparison error,
wherein the voltage at the common node is based on one or more capacitors of the first array being coupled to a reference voltage or to the ground potential and the voltage at the other common node is based on one or more capacitors of the second array being coupled to the reference voltage or to the ground potential, the one or more capacitors of the first array and/or the one or more capacitors of the second array being coupled to the reference voltage or to the ground potential in pairs, each pair comprising a capacitor of the first array and an associated capacitor of the second array, according to a successive approximation binary search algorithm.

14. The ADC of claim 13 , the SA capacitor array further comprising a second comparator arranged to compare an output of a combination of the first array and the second array to ground, and to output a digital value based on the comparison.

15. The ADC of claim 13 , the SA capacitor array further comprising a second comparator arranged to compare a voltage at a common node associated with the first array of capacitors to a voltage at another common node associated with the second array or capacitors, and to output a digital value based on the comparison.

16. A method, comprising:
coupling a first terminal of a plurality of non-binary weighted capacitances at a common node in a descending order of capacitance values according to a predetermined numerical pattern to form a first non-binary weighted successive approximation capacitor array;
coupling a first terminal of another plurality of non-binary weighted capacitances at another common node to form a second non-binary weighted successive approximation capacitor array, the second non-binary weighted successive approximation capacitor array substantially identical to the first non-binary weighted successive approximation capacitor array;
coupling the common node of the first array to the other common node of the second array and to a first input of a comparator;
sampling an analog input voltage by coupling the analog input voltage from a second terminal of each capacitance of the first array to a second terminal of each capacitance of the second array;
resetting the first input of the comparator to a reset voltage and setting the first input of the comparator to a high impedance state;
coupling the second terminal of each capacitance of the first array to a reference voltage and the second terminal of each capacitance of the second array to ground;
coupling the second terminal of a capacitance of the second array representing a most signif

Assignees

• Infineon Technologies Ag

Inventors

• Draxelmayr Dieter

Classifications

• H03M1/0692 Primary

  using a diminished radix representation, e.g. radix 1.95 · CPC title

• H03M1/468

  in which the input S/H circuit is merged with the feedback DAC array · CPC title

• H03M1/00

  Analogue/digital conversion; Digital/analogue conversion (conversion of analogue values to or from differential modulation H03M3/00) · CPC title

• H03M1/804

  with charge redistribution · CPC title

• H03M1/12

  Analogue/digital converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title