Control circuits of collector current of substrate bipolar junction transistors and circuits of compensating for base current for generating a proportional to absolute temperature (PTAT) voltage using the control circuits

Patent metadata

Field	Value
Publication number	US-9912330-B2
Application number	US-201715421055-A
Country	US
Kind code	B2
Filing date	Jan 31, 2017
Priority date	Jul 1, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A circuit for controlling a collector current of a substrate bipolar junction transistor (BJT) is provided. The circuit includes a first current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the substrate BJT, a current transmitter configured to transmit the first mirroring base current, a second current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter and configured to supply the second mirroring base current to an emitter of the substrate BJT, and a current source configured to supply a drive current corresponding to a collector current of the substrate BJT to the emitter of the substrate BJT.

First claim

What is claimed is:

1. A circuit for controlling a collector current of a substrate bipolar junction transistor (BJT), the circuit comprising:
a first current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the substrate BJT;
a current transmitter configured to transmit the first mirroring base current;
a second current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter and configured to supply the second mirroring base current to an emitter of the substrate BJT; and
a current source configured to supply a drive current corresponding to a collector current of the substrate BJT to the emitter of the substrate BJT.

2. The circuit of claim 1 , wherein the substrate BJT is a PNP BJT.

3. The circuit of claim 2 , wherein:
the first current mirror includes a first NMOS transistor and a second NMOS transistor;
a gate bias voltage is applied to gates of the first and second NMOS transistors, and sources of the first and second NMOS transistors are coupled to a ground terminal;
a drain of the first NMOS transistor is coupled to a base of the substrate BJT, and a drain of the second NMOS transistor is coupled to the current transmitter; and
a drain voltage of the first NMOS transistor is equal to a drain voltage of the second NMOS transistor.

4. The circuit of claim 3 , further comprising an operational amplifier configured to provide a negative feedback loop so that the drain voltages of the first and second NMOS transistors have the same level.

5. The circuit of claim 4 , wherein:
a non-inverting input terminal and an inverting input terminal of the operational amplifier are coupled to the drain of the first NMOS transistor and the drain of the second NMOS transistor, respectively; and
an output terminal of the operational amplifier is coupled to the current transmitter.

6. The circuit of claim 5 , wherein the current transmitter includes a first PMOS transistor having a gate coupled to the output terminal of the operational amplifier, a source coupled to the second current mirror, and a drain coupled to the drain of the second NMOS transistor.

7. The circuit of claim 6 , wherein:
the second current mirror includes a second PMOS transistor and a third PMOS transistor;
gates of the second and third PMOS transistors are coupled to each other, and sources of the second and third PMOS transistors are coupled to a supply voltage terminal;
a drain of the second PMOS transistor is coupled to a source of the first PMOS transistor;
a drain of the third PMOS transistor is coupled to the emitter of the substrate BJT; and
the second PMOS transistor has a diode-connected structure in which the gate and the drain of the second PMOS transistor are coupled to each other.

8. A circuit for compensating a base current for generating a PTAT voltage, the circuit comprising:
a first current mirror configured to supply a first collector current corresponding to a collector current of a first substrate bipolar junction transistor (BJT) to an emitter of the first substrate BJT;
a second current mirror configured to generate a first mirroring base current corresponding to a replicate current of a base current of the first substrate BJT;
a current transmitter configured to transmit the first mirroring base current;
a third current mirror configured to generate a second mirroring base current corresponding to a replicate current of the first mirroring base current received from the current transmitter to supply the second mirroring base current to the emitter of the first substrate BJT and configured to generate a third mirroring base current having an amount which is equal to “N” (wherein, “N” denotes a natural number which is greater than one) times an amount of the first mirroring base current to supply the third mirroring base current to an emitter of a second substrate BJT; and
a second collector current transmitter configured to supply a second collector current to the emitter of the second substrate BJT where the second collector current amount is equal to “N” times an amount of the first collector current.

9. The circuit of claim 8 , wherein the first and second substrate BJTs are PNP BJTs.

10. The circuit of claim 9 , wherein:
the first current mirror includes a first PMOS transistor and a second PMOS transistor;
gates of the first and second PMOS transistors are coupled to each other, and sources of the first and second PMOS transistors are coupled to a supply voltage terminal;
the first PMOS transistor has a diode-connected structure in which the gate and the drain of the first PMOS transistor are coupled to each other; and
a drain of the second PMOS transistor is coupled to the emitter of the first substrate BJT.

11. The circuit of claim 10 , further comprising a current source coupled between the drain of the first PMOS transistor and a ground terminal.

12. The circuit of claim 10 , wherein:
the second current mirror includes a first NMOS transistor and a second NMOS transistor;
a gate bias voltage is applied to gates of the first and second NMOS transistors, and sources of the first and second NMOS transistors are coupled to a ground terminal;
a drain of the first NMOS transistor is coupled to a base of the first substrate BJT, and a drain of the second NMOS transistor is coupled to the current transmitter; and
a drain voltage of the first NMOS transistor is equal to a drain voltage of the second NMOS transistor.

13. The circuit of claim 12 , further comprising an operational amplifier configured to provide a negative feedback loop so that the drain voltages of the first and second NMOS transistors have the same level.

14. The circuit of claim 13 , wherein:
a non-inverting input terminal and an inverting input terminal of the operational amplifier are coupled to the drain of the first NMOS transistor and the drain of the second NMOS transistor, respectively; and
an output terminal of the operational amplifier is coupled to the current transmitter.

15. The circuit of claim 14 , wherein the current transmitter includes a third PMOS transistor having a gate coupled to the output terminal of the operational amplifier, a source coupled to the third current mirror, and a drain coupled to the drain of the second NMOS transistor.

16. The circuit of claim 15 , wherein:
the third current mirror includes a fourth PMOS transistor, a fifth PMOS transistor and a sixth PMOS transistor;
gates of the fourth, fifth and sixth PMOS transistors are coupled to each other, and sources of the fourth, fifth and sixth PMOS transistors are coupled to a supply voltage terminal;
a drain of the fourth PMOS transistor is coupled to the emitter of the first substrate BJT;
a drain of the fifth PMOS transistor is coupled to a source of the third PMOS transistor;
a drain of the sixth PMOS transistor is coupled to the emitter of the second substrate BJT; and
the fifth PMOS transistor has a diode-connected structure in which the gate and the drain of the fifth PMOS transistor are coupled to each other.

17. The circuit of claim 16 , wherein the sixth PMOS transistor has a current drivability which is equal to “N” times a current drivability of the fifth PMOS transistor.

18. The circuit of claim 17 , wherein the second collector current transmitter includes a seventh PMOS transistor having a current drivability which is equal to “N” times a current drivability of the second PMO

Assignees

• Sk Hynix Inc
• Nat Univ Chonbuk Ind Coop Found

Inventors

• Kim Hee Jun
• Lee Sang Won
• Jeong Hang Geun

Classifications

• H10D84/401

  Combinations of FETs or IGBTs with BJTs · CPC title

• H03K17/567 Primary

  Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT · CPC title

• H01L27/0623

  Electricity · mapped topic

• H01L29/0821

  Electricity · mapped topic

• H10D62/137

  Collector regions of BJTs · CPC title