Start-up circuit and method using a depletion mode transistor

Patent metadata

Field	Value
Publication number	US-9912228-B2
Application number	US-201615228682-A
Country	US
Kind code	B2
Filing date	Aug 4, 2016
Priority date	Aug 29, 2012
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A start-up circuit includes an input node, an output node, a reference node, and a depletion mode field-effect transistor (FET) having a first terminal coupled to the input node, a second terminal coupled to the output node, and a gate terminal. A Zener diode has a cathode coupled to the gate terminal of the FET and an anode coupled to the reference node. A first capacitor is coupled in parallel with the Zener diode, a first resistor is coupled between the gate terminal of the FET and the input node, and a second resistor is coupled between the second terminal of the FET and the reference node. The FET and the second resistor are configured to generate an output voltage on the output node, the output voltage being based on an input voltage on the input node and capped at a value below a peak value of the input voltage.

First claim

What is claimed is:

1. A start-up circuit comprising:
an input node, an output node, and a reference node;
a depletion mode field-effect transistor (FET) having a first terminal coupled to the input node, a second terminal coupled to the output node, and a gate terminal;
a Zener diode having a cathode coupled to the gate terminal of the FET and an anode coupled to the reference node;
a first capacitor coupled in parallel with the Zener diode;
a first resistor coupled between the gate terminal of the FET and the input node; and
a second resistor coupled between the second terminal of the FET and the reference node,
wherein
the first resistor and the Zener diode are configured to generate a gate voltage at the gate terminal as part of an electrically continuous current path from the input node to the reference node, and
the FET and the second resistor are configured to generate an output voltage on the output node, the output voltage being based on an input voltage on the input node and capped at a value below a peak value of the input voltage.

2. The start-up circuit of claim 1 , further comprising:
a second capacitor coupled between the output node and the reference node.

3. The start-up circuit of claim 2 , further comprising:
a second diode coupled between the gate terminal of the FET and the input node.

4. The start-up circuit of claim 3 , further comprising:
a third diode having an anode coupled to the output node and a cathode coupled to the second terminal of the FET.

5. The start-up circuit of claim 4 , further comprising:
a fourth diode having an anode coupled to the output node.

6. The start-up circuit of claim 5 , further comprising:
a fifth diode having an anode coupled to a cathode of the fourth diode, and a cathode configured to receive power; and
a third capacitor coupled between the anode of the fifth diode and the reference node.

7. The start-up circuit of claim 1 , wherein the FET is an N-channel depletion mode FET.

8. The start-up circuit of claim 1 , wherein the FET has a voltage rating of 400 V to 800 V.

9. A start-up circuit comprising:
a first power section comprising a depletion mode transistor, the first power section being configured to receive a first input voltage at an input node and generate a first node voltage from the first input voltage, the first node voltage having a capped voltage value based on a threshold voltage of the depletion mode transistor;
a second power section configured to generate a second node voltage from a second input voltage;
a selector configured to
select one of the first node voltage or the second node voltage, and output an output voltage on an output node, the output voltage being based on the selected first node voltage or second node voltage, and
when the second node voltage is selected, electrically isolate the depletion mode transistor from the output node; and

a first capacitor configured to sustain the output voltage above a reference voltage value during periods in which the first node voltage drops below the capped voltage value.

10. The start-up circuit of claim 9 , wherein the first power section further comprises a Zener diode coupled with a gate of the PET, and the capped voltage value is further based on a Zener diode voltage of the Zener diode.

11. The start-up circuit of claim 10 , wherein the capped voltage value is the sum of the Zener diode voltage and a magnitude of the threshold voltage of the depletion mode transistor.

12. The start-up circuit of claim 9 , wherein the selector comprises a first diode configured to prevent discharge of the first capacitor during the periods in which the first node voltage drops below the capped voltage value.

13. The start-up circuit of claim 9 , wherein the first power section further comprises a second capacitor configured to maintain a gate voltage of the depletion mode transistor during the periods in which the first node voltage drops below the capped voltage value.

14. The start-up circuit of claim 13 , wherein the first power section further comprises a diode configured to prevent discharging of the second capacitor during the periods in which the first node voltage drops below the capped voltage value.

15. The start-up circuit of claim 9 , wherein
the depletion mode transistor is configured as a source follower, and
the first power section further comprises a resistor configured to maintain a predetermined bandwidth of the source follower.

16. A method of generating a start-up voltage, the method comprising:
receiving, at a first node of a start-up circuit, an AC rectified voltage;
generating, by a depletion mode field-effect transistor (FET), a first voltage from the AC rectified voltage;
capping, with the depletion mode FET, the first voltage at a value below a peak value of the AC rectified voltage;
receiving, at a second node of the start-up circuit, a second voltage;
selecting the higher of the first voltage or the second voltage; and
outputting an output voltage on an output node based on the selected first voltage or second voltage,
wherein outputting the second voltage comprises electrically isolating the depletion mode FET from the output node.

17. The method of claim 16 , wherein capping the first voltage at the value below the peak value of the rectified voltage comprises operating the depletion mode FET in a saturation region.

18. The method of claim 16 , further comprising providing a constant voltage at a gate terminal of the depletion mode FET.

19. The method of claim 18 , wherein providing the constant voltage at the gate terminal of the depletion mode FET comprises maintaining a Zener voltage of a Zener diode coupled to the gate terminal of the depletion mode FET.

20. The method of claim 16 , further comprising sustaining the output voltage above a reference voltage value during periods in which the first voltage drops below the capped voltage value.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Al Shyoukh Mohammad
• Neyra Percy

Classifications

• H02M1/36 Primary

  Means for starting or stopping converters · CPC title

• H02M3/33523

  with galvanic isolation between input and output of both the power stage and the feedback loop · CPC title

• H05B33/0815

  Electricity · mapped topic

• H05B45/385

  using flyback topology · CPC title