Template battery and circuit design thereof

Patent metadata

Field	Value
Publication number	US-9912176-B2
Application number	US-201514958877-A
Country	US
Kind code	B2
Filing date	Dec 3, 2015
Priority date	Dec 3, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A template battery comprises one or more layers that fill into a dead space on a substrate. The substrate comprises one or more components. The one or more layers of the template battery are arranged as a mirror image of the topography of the one or more components on the substrate. A template battery is coupled to a charge controller. The charge controller is coupled to the main battery.

First claim

What is claimed is:

1. A battery comprising:
a plurality of layers, wherein at least a subset of the plurality of layers comprise openings to form a first topography of the battery, the openings correspond to geometries of one or more components mounted on a substrate of a computing device, the one or more components mounted on the substrate form a second topography,
wherein the first topography comprises a compliment of the second topography such that the openings of the plurality of layers, when the plurality of layers are overlaid on the substrate, are to be at least partially filled by the one or more components on the substrate.

2. The battery of claim 1 , wherein the plurality of layers represent respective levels of a terrain map of the one or more components on the substrate.

3. The battery of claim 1 , wherein the plurality of layers comprise:
a first electrode layer;
a second electrode layer; and
a separator layer coupled to the first electrode layer and the second electrode layer.

4. The battery of claim 1 , wherein at least some of the openings of the plurality of layers expose the one or more components.

5. The battery of claim 1 , wherein at least some of the layers are coupled in parallel.

6. The battery of claim 1 , wherein the plurality of layers comprise an energy storage device layer, a battery layer, or both.

7. The battery of claim 1 , wherein the plurality of layers are thicker over a first portion of the substrate than over a second portion of the substrate, and wherein the first portion is lower than the second portion.

8. A system comprising:
a substrate;
one or more components mounted on the substrate;
a first battery;
a charge controller coupled to the first battery; and
a second battery coupled to the charge controller,
wherein the first battery comprises a plurality of layers, at least a subset of the plurality of layers comprise openings, the openings correspond to geometries of the one or more components mounted on a substrate of a computing device, the one or more components mounted on the substrate form a second topography, and the openings are to be at least partially filled by the one or more components when the plurality of layers are overlaid on the substrate.

9. The system of claim 8 , wherein the first battery is coupled to a ground.

10. The system of claim 8 , wherein first battery is coupled to a power supply.

11. The system of claim 8 , further comprising a processing system coupled to the charge controller.

12. The system of claim 8 , further comprising a third battery coupled to the first battery.

13. The system of claim 8 , further comprising a protection circuit coupled to the first battery.

14. A method to provide a battery, comprising:
generating a plurality of layers of the battery, wherein at least a subset of the plurality of layers comprise openings to form a first topography of the battery, the openings correspond to geometries of one or more components mounted on a substrate of a computing device, the one or more components mounted on the substrate form a second topography; and
arranging the plurality of layers on the substrate, wherein the first topography comprises a compliment of the second topography such that the openings of the plurality of layers, and the plurality of layers are arranged on the substrate to at least partially fill each of the openings with the one or more components on the substrate.

15. The method of claim 14 , further comprising
determining the second topography from a terrain map for the one or more components on the substrate; and
wherein arranging the plurality of layers on the substrate comprises stacking the plurality of layers as levels of the terrain map.

16. The method of claim 14 , wherein the plurality of layers comprise:
a first electrode layer;
a second electrode layer; and
a separator layer coupled to the first electrode layer and the second electrode layer.

17. The method of claim 14 , further comprising forming the openings in the plurality of layers, wherein at least some of the openings are to expose at least one of the one or more components.

18. The method of claim 14 , further comprising coupling at least some of the plurality of layers in parallel.

19. The method of claim 14 ,
wherein the plurality of layers are thicker over a first portion of the substrate than over a second portion of the substrate, and
wherein the first portion is lower than the second portion.

Assignees

• Intel Corp

Inventors

• Matsumura Naoki
• Keates Andrew
• Siili Arto
• Schline Jeffrey M

Classifications

• H02J7/50

  acting upon multiple batteries simultaneously or sequentially · CPC title

• H01M10/425

  Structural combination with electronic components, e.g. electronic circuits integrated to the outside of the casing (printed circuits H05K1/00) · CPC title

• H01M2010/4271

  Battery management systems including electronic circuits, e.g. control of current or voltage to keep battery in healthy state, cell balancing · CPC title

• H02J7/0013 Primary

  Electricity · mapped topic

• H01M10/0436 Primary

  Small-sized flat cells or batteries for portable equipment · CPC title