Vertical transistor and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-9911848-B2
Application number	US-201414473215-A
Country	US
Kind code	B2
Filing date	Aug 29, 2014
Priority date	Aug 29, 2014
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A vertical transistor includes a source-channel-drain structure, a gate and a gate dielectric layer. The source-channel-drain structure includes a source, a drain over the source and a channel between the source and the drain. The gate surrounds a portion of the channel. The gate is configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor. In some embodiments, the vertical transistor further includes an ILD configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

First claim

What is claimed is:

1. A vertical transistor, comprising:
a source-channel-drain nanowire structure comprising a source, a drain over the source, and a channel between the source and the drain;
a gate surrounding a portion of the channel, the gate being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the gate being configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is a p-channel vertical transistor; and
a gate dielectric layer between the channel and the gate,
wherein the gate dielectric layer is in contact with a bottom surface of the drain.

2. The vertical transistor of claim 1 , wherein the gate configured to provide the compressive strain substantially along the extending direction of the channel comprises titanium-aluminum (TiAl), titanium-aluminum carbide (TiAlC) or a combination thereof.

3. The vertical transistor of claim 1 , wherein the gate configured to provide the tensile strain substantially along the extending direction of the channel comprises tungsten (W).

4. The vertical transistor of claim 1 , further comprising an inter-layer dielectric (ILD) over the gate and in contact with the gate dielectric layer and surrounding another portion of the channel, and the ILD is configured to provide tensile strain substantially along the extending direction of the channel when the vertical transistor is the n-channel vertical transistor, or the ILD is configured to provide compressive strain substantially along the extending direction of the channel when the vertical transistor is the p-channel vertical transistor.

5. The vertical transistor of claim 4 , wherein the drain has a width greater than a width of the channel.

6. The vertical transistor of claim 5 , wherein the width of the drain is greater than a bottom width of the drain.

7. The vertical transistor of claim 6 , wherein a width difference between the width of the drain and the bottom width of the drain is lower than or equal to about 10 nm.

8. The vertical transistor of claim 1 , wherein the vertical transistor comprises a plurality of the source-channel-drain nanowire structures substantially parallel to one another.

9. The vertical transistor of claim 1 , wherein the bottom surface of the drain has an angled side surface connected to a side surface of the channel.

10. A vertical transistor, comprising:
a source-channel-drain nanowire structure comprising a source, a drain over the source, and a channel between the source and the drain;
a gate surrounding a portion of the channel;
a gate dielectric layer between the channel and the gate, wherein the gate dielectric layer is in contact with a bottom surface of the drain; and
an ILD over the gate and in contact with the gate dielectric layer and surrounding another portion of the channel, the ILD being configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the ILD being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

11. The vertical transistor of claim 10 , wherein the drain has a width greater than a width of the channel.

12. The vertical transistor of claim 11 , wherein the width of the drain is greater than a bottom width of the drain.

13. The vertical transistor of claim 12 , wherein a width difference between the width of the drain and the bottom width of the drain is lower than or equal to about 10 nm.

14. The vertical transistor of claim 10 , wherein the bottom surface of the drain has a horizontal bottom surface and an angled side surface surrounding the horizontal bottom surface, and an included angle between the horizontal bottom surface and the angled side surface is greater than 90-degrees and smaller than 180-degrees.

15. The vertical transistor of claim 14 , wherein a height difference between a highest point of the angled side surface and a lowest point of the angled side surface is lower than or equal to about 30 nm.

16. The vertical transistor of claim 14 , wherein the included angle between the horizontal bottom surface and the angled side surface is ranging from about 105-degrees to about 170-degrees.

17. The vertical transistor of claim 10 , further comprising a spacer surrounding the drain.

18. The vertical transistor of claim 17 , wherein the spacer has a thickness of about 2 to about 15 nm.

19. The vertical transistor of claim 17 , wherein the spacer is over and in contact with the ILD.

20. A vertical transistor, comprising:
a source-channel-drain structure comprising a source, a drain over the source, and a channel between the source and the drain;
a gate surrounding a portion of the channel;
a gate dielectric layer between the channel and the gate;
a spacer surrounding the drain, wherein a height of a lowest point of a bottom surface of the spacer is as same as a height of a lowest point of a bottom surface of the drain; and
an ILD over the gate and in contact with the gate dielectric layer and surrounding another portion of the channel, the ILD being configured to provide tensile strain substantially along an extending direction of the channel when the vertical transistor is an n-channel vertical transistor, or the ILD being configured to provide compressive strain substantially along an extending direction of the channel when the vertical transistor is a p-channel vertical transistor.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Diaz Carlos H
• Wang Chih Hao
• Lien Wai Yi
• Yang Kai Chieh
• Tang hao ling

Classifications

• B82Y40/00

  Manufacture or treatment of nanostructures · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/495

  Electricity · mapped topic

• H01L29/775

  Electricity · mapped topic

• H01L21/823885

  Electricity · mapped topic