Semiconductor device and method of forming the same

Patent metadata

Field	Value
Publication number	US-9911787-B2
Application number	US-201615187929-A
Country	US
Kind code	B2
Filing date	Jun 21, 2016
Priority date	Oct 20, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A semiconductor device includes an active region defining an isolation region. First and second cell interconnection structures are on the active region and the isolation region, and have line shapes that are parallel to each other. An isolation pattern is on the active region and the isolation region. The isolation pattern is between the first and second cell interconnection structures. Contact structures are between the first and second cell interconnection structures. The contact structures are at both sides of the isolation pattern and overlap the active region. Insulating patterns are between the first and second cell interconnection structures. The insulating patterns are at both sides of the isolation pattern and overlap the isolation region. Common source regions are under the first and second cell interconnection structures. The common source regions are in the active region. An isolating gate pattern that has a line shape is under the isolation pattern.

First claim

What is claimed is:

1. A semiconductor device comprising:
first and second isolating gate patterns configured to have a line shape extending in a first direction;
first and second cell transistors disposed between the first and second isolating gate patterns, the first and second cell transistors sharing a common source region, the first cell transistor including the common source region, a first cell drain region, and a first cell gate line, and the second cell transistor including the common source region, a second cell drain region, and a second cell gate line;
a first isolation pattern disposed on the first isolating gate pattern and configured to have a line shape extending in the first direction;
a second isolation pattern disposed on the second isolating gate pattern and configured to have a line shape extending in the first direction;
a cell interconnection structure disposed between the first and second isolation patterns, disposed on the common source region, and configured to have a line shape extending in the first direction;
a first contact structure disposed on the first cell drain region; and
a second contact structure disposed on the second cell drain region.

2. The semiconductor device of claim 1 , further comprising:
an active region configured to have a line shape extending in a second direction that is substantially perpendicular to the first direction.

3. The semiconductor device of claim 2 , wherein the first and second cell gate lines are buried in the active region.

4. The semiconductor device of claim 3 , wherein at least one of the first and second isolating gate patterns include an isolating gate line buried in the active region.

5. The semiconductor device of claim 3 , wherein the first and second cell gate lines have a line shape extending in the first direction.

6. The semiconductor device of claim 1 , wherein the first isolating gate pattern includes a first isolating gate line and a first isolating gate capping pattern that are sequentially stacked, and the second isolating gate pattern includes a second isolating gate line and a second isolating gate capping pattern that are sequentially stacked.

7. The semiconductor device of claim 6 , wherein the first isolation pattern is in contact with the first isolating gate capping pattern and the second isolation pattern is in contact with the second isolating gate capping pattern.

8. The semiconductor device of claim 6 , further comprising:
a first cell gate capping pattern disposed on the first cell gate line,
wherein an uppermost portion of the first cell gate capping pattern is higher than an uppermost portion of the first isolating gate capping pattern.

9. The semiconductor device of claim 1 , further comprising:
a first data storage element disposed on the first contact structure; and
a second data storage element disposed on the second contact structure.

10. The semiconductor device of claim 9 , further comprising:
a bit line disposed on the first and second data storage elements and configured to have a line shape extending in the first direction.

11. A semiconductor device comprising:
cell isolation regions configured to define cell active regions;
a pair of isolating gate lines disposed in a pair of isolating gate trenches that intersect the cell active regions and the cell isolation regions;
a pair of cell gate lines disposed in a pair of cell gate trenches that intersect the cell active regions and the cell isolation regions, wherein the pair of cell gate lines are disposed between the pair of isolating gate lines;
a pair of isolation patterns disposed on the pair of isolating gate lines;
a cell interconnection structure disposed between the pair of isolation patterns and on the cell active regions and the cell isolation regions;
cell contact structures disposed between the pair of isolation patterns and the cell interconnection structure and on the cell active regions; and
insulating patterns disposed between the pair of isolation patterns and the cell interconnection structure and on the cell isolation regions.

12. The semiconductor device of claim 11 , wherein the pair of isolating gate lines and the pair of cell gate lines have a line shape extending in a first direction, and the cell active regions and the cell isolation regions have a line shape extending in a second direction substantially perpendicular to the first direction.

13. The semiconductor device of claim 12 , wherein the cell interconnection structure and the pair of isolation patterns have a line shape extending in the first direction.

14. The semiconductor device of claim 12 , wherein the cell interconnection structure includes a contact portion in contact with the cell active region between the pair of cell gate lines and an interconnection portion on the contact portion, wherein the contact portion of the cell interconnection structure has a line shape extending in the first direction.

15. The semiconductor device of claim 11 , further comprising:
a peripheral isolation region configured to define a peripheral active region;
a peripheral gate structure configured to intersect the peripheral active region;
peripheral source and drain regions disposed in the peripheral active region at opposite sides of the peripheral gate structure;
peripheral contact structures disposed on the peripheral source and drain regions; and
cell drain regions disposed in the cell active regions under the cell contact structures,
wherein the peripheral contact structures include a peripheral contact silicide layer disposed on the peripheral source, and drain regions and peripheral contact conductive patterns disposed on the peripheral contact silicide layer, and the cell contact structures include a cell lower contact pattern disposed on the cell drain region, a cell contact silicide layer disposed on the cell lower contact pattern, and a cell upper contact pattern disposed on the cell contact silicide layer,
wherein the cell contact silicide layer and the peripheral contact silicide layer include a same material, and the cell upper contact pattern and the peripheral contact conduction pattern include a same material.

16. A semiconductor device comprising:
a plurality of interconnection structures on an active region and on an isolation region, the plurality of interconnection structures extending in a first direction;
an isolation pattern on the active region and the isolation region, the isolation pattern being between two of the plurality of interconnection structures and extending in the first direction; and
an isolating gate pattern under the isolation pattern and extending in the first direction,
wherein the active region and the isolation region extend in a second direction substantially perpendicular to the first direction.

17. The semiconductor device of claim 16 , further comprising:
contact structures between the two of the plurality of interconnection structures, at opposite sides of the isolation pattern, and overlapping the active region.

18. The semiconductor device of claim 17 , further comprising:
insulating patterns between the two of the plurality of interconnection structures, at the opposite sides of the isolation pattern, and overlapping the isolation region.

19. The semiconductor device of claim 18 , further comprising:
common source regions under the plurality of interconnection structures and in the active region.

20. The semiconductor device of claim 16 , wherein the isolating gate pattern is in an isolating g

Assignees

• Suh Kiseok
• Koh Gwanhyeob
• Song Yoonjong
• Samsung Electronics Co Ltd

Inventors

• Suh Kiseok
• Koh Gwanhyeob
• Song Yoonjong

Classifications

• H01L43/08

  Electricity · mapped topic

• H01L43/12

  Electricity · mapped topic

• H01L43/02

  Electricity · mapped topic

• H01L27/228 Primary

  Electricity · mapped topic

• H10D1/00 Primary

  Resistors, capacitors or inductors · CPC title