Nonvolatile nanotube diodes and nonvolatile nanotube blocks and systems using same and methods of making same

Patent metadata

Field	Value
Publication number	US-9911743-B2
Application number	US-83585207-A
Country	US
Kind code	B2
Filing date	Aug 8, 2007
Priority date	May 9, 2005
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Under one aspect, a method of making a nanotube switch includes: providing a substrate having a first conductive terminal; depositing a multilayer nanotube fabric over the first conductive terminal; and depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals. In some embodiments, the first and second conductive terminals and the multilayer nanotube fabric are lithographically patterned so as to each have substantially the same lateral dimensions, e.g., to each have a substantially circular or rectangular lateral shape. In some embodiments, the multilayer nanotube fabric has a thickness from 10 nm to 200 nm, e.g., 10 nm to 50 nm. The structure may include an addressable diode provided under the first conductive terminal or deposited over the second terminal.

First claim

What is claimed is:

1. A method of making a nanotube switch, comprising:
providing a substrate having a first conductive terminal;
depositing a multilayer nanotube fabric over the first conductive terminal; and
depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a nanotube configuration with a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals;
wherein the multilayer nanotube fabric is directly and permanently electrically coupled to both the first and second conductive and said multilayer nanotube fabric is adjustable between at least two resistive states responsive to control circuitry.

2. The method of claim 1 , further comprising lithographically patterning the first and second conductive terminals and the multilayer nanotube fabric so as to each have substantially the same lateral dimensions.

3. The method of claim 2 , wherein the first and second conductive terminals and the multilayer nanotube fabric each have a substantially circular lateral shape.

4. The method of claim 2 , wherein the first and second conductive terminals and the multilayer nanotube fabric each have a substantially rectangular lateral shape.

5. The method of claim 2 , wherein the first and second conductive terminals and the multilayer nanotube fabric each have lateral dimensions of between about 200 nm and about 22 nm.

6. The method of claim 2 , wherein F is a dimension of a technology node and wherein the first and second conductive terminals and the multilayer nanotube fabric each has a lateral dimension of the F.

7. The method of claim 2 , wherein the first and second conductive terminals and the multilayer nanotube fabric each have a lateral dimension of less than 10 nm.

8. The method of claim 1 , wherein the multilayer nanotube fabric has a thickness between about 10 nm and about 200 nm.

9. The method of claim 1 , wherein the multilayer nanotube fabric has a thickness between about 10 nm and about 50 nm.

10. The method of claim 1 , wherein the substrate comprises a diode under the first conductive terminal, the diode being addressable by control circuitry.

11. The method of claim 10 , further comprising lithographically patterning the first and second conductive terminals, the multilayer nanotube fabric, and the diode so as to each have substantially the same lateral dimensions.

12. The method of claim 10 , further comprising providing a second diode over the second conductive terminal, depositing a third conductive terminal over the second diode, depositing a second multilayer nanotube fabric over the third conductive terminal, and depositing a fourth conductive terminal over the second multilayer nanotube fabric.

13. The method of claim 12 , further comprising lithographically patterning the multilayer nanotube fabrics, the diodes, and the conductive terminals so as to each have substantially the same lateral dimensions.

14. The method of claim 10 , wherein the diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of conductor.

15. The method of claim 10 , wherein the diode comprises a layer of N+ polysilicon, a layer of N polysilicon, and a layer of P polysilicon.

16. The method of claim 1 , further comprising providing a diode over the second conductive terminal, the diode being addressable by control circuitry.

17. The method of claim 16 , further comprising annealing the diode at a temperature exceeding 700° C.

18. The method of claim 16 , further comprising lithographically patterning the first and second conductive terminals, the multilayer nanotube fabric, and the diode so as to each have substantially the same lateral dimensions.

19. The method of claim 1 , wherein the substrate comprises a semiconductor field effect transistor, at least a portion of which is under the first conductive terminal, the semiconductor field effect transistor being addressable by control circuitry.

20. The method of claim 1 , wherein depositing the multilayer nanotube fabric comprises spraying nanotubes dispersed in a solvent onto the first conductive terminal.

21. The method of claim 1 , wherein depositing the multilayer nanotube fabric comprises spin coating nanotubes dispersed in a solvent onto the first conductive terminal.

22. The method of claim 1 , wherein depositing the multilayer nanotube fabric comprises depositing a mixture of nanotubes and a matrix material dispersed in a solvent onto the first conductive terminal.

23. The method of claim 22 , further comprising removing the matrix material after depositing the second conductive terminal.

24. The method of claim 22 , wherein the matrix material comprises polypropylene carbonate.

25. The method of claim 1 , wherein the first and second conductive terminals each comprise a conductive material independently selected from the group consisting of Ru, Ti, Cr, Al, Al(Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi x , and TiSi x .

26. The method of claim 1 , further comprising depositing a porous dielectric material on the multilayer nanotube fabric.

27. The method of claim 26 , wherein the porous dielectric material comprises one of a spin-on glass and a spin-on low-κ dielectric.

28. The method of claim 1 , further comprising depositing a nonporous dielectric material on the multilayer nanotube fabric.

29. The method of claim 28 , wherein the nonporous dielectric material comprises a high-κ dielectric.

30. The method of claim 28 , wherein the nonporous dielectric material comprises hafnium oxide.

31. The method of claim 1 , further comprising providing a word line in electrical communication with the second conductive terminal.

32. A method of making a nanotube diode, comprising:
providing a substrate having a first conductive terminal;
depositing a multilayer nanotube fabric over the first conductive terminal;
depositing a second conductive terminal over the multilayer nanotube fabric, the nanotube fabric having a nanotube configuration with a thickness, density, and composition selected to prevent direct physical and electrical contact between the first and second conductive terminals;
providing a diode in electrical contact with one of the first and second conductive terminals;
wherein the multilayer nanotube fabric is directly and permanently electrically coupled to both the first and second conductive and said multilayer nanotube fabric is adjustable between at least two resistive states responsive to control circuitry.

33. The method of claim 32 , further comprising providing the diode after depositing the multilayer nanotube fabric.

34. The method of claim 33 , further comprising annealing the diode at a temperature exceeding 700° C.

35. The method of claim 32 , further comprising positioning the diode over and in electrical contact with the second conductive terminal.

36. The method of claim 32 , further comprising positioning the diode under and in electrical contact with the first conductive terminal.

37. The method of claim 32 , further comprising lithographically patterning the first and second conductive t

Assignees

• Bertin Claude L
• Rueckes Thomas
• Huang X M Henry
• Sivarajan Ramesh
• Ghenciu Eliodor G
• Konsek Steven L
• Meinhold Mitchell
• Ward Jonathan W
• Brock Darren K
• Nantero Inc

Inventors

• Bertin Claude L
• Rueckes Thomas
• Huang X M Henry
• Sivarajan Ramesh
• Ghenciu Eliodor G
• Konsek Steven L
• Meinhold Mitchell
• Ward Jonathan W
• Brock Darren K

Classifications

• G11C2213/19

  Memory cell comprising at least a nanowire and only two terminals · CPC title

• G11C2213/71

  Three dimensional array · CPC title

• G11C2213/72

  Array wherein the access device being a diode · CPC title

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• G11C13/025 Primary

  using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes · CPC title