Transient voltage suppressor and manufacture method thereof

Patent metadata

Field	Value
Publication number	US-9911730-B2
Application number	US-201615268773-A
Country	US
Kind code	B2
Filing date	Sep 19, 2016
Priority date	Sep 22, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A transient voltage suppressor can include: a semiconductor substrate; a first buried layer of a first type formed in and on the semiconductor substrate; a second buried layer of a second type formed in a first region of the first buried layer; a first epitaxial region of the second type formed on the second buried layer and a second epitaxial region of the first type formed on a second region of the first buried layer; a first doped region of the first type formed in the first epitaxial region and a second doped region of the second type formed in the second epitaxial region; a conductive channel extending from a surface of the second epitaxial region into the first buried layer; and a first electrode connected to the conductive channel, a second electrode connected to the first doped region, and a third electrode connected to the second doped region.

First claim

What is claimed is:

1. A transient voltage suppressor, comprising:
a) a semiconductor substrate;
b) a first buried layer of a first doped type formed in and on said semiconductor substrate;
c) a second buried layer of a second doped type formed in a first region of said first buried layer;
d) a first epitaxial region of said second doped type formed on said second buried layer and a second epitaxial region of said first doped type formed on a second region of said first buried layer;
e) a first doped region of said first doped type formed in said first epitaxial region and a second doped region of said second doped type formed in said second epitaxial region;
f) a conductive channel extending from a surface of said second epitaxial region into said first buried layer; and
g) a first electrode connected to said conductive channel, a second electrode connected to said first doped region, and a third electrode connected to said second doped region.

2. The transient voltage suppressor of claim 1 , wherein:
a) a PN junction of a zener diode or a punch-through diode is formed between said first buried layer and said second buried layer;
b) a PN junction of a first diode is formed between said first epitaxial region and said first doped region; and
c) a PN junction of a second diode is formed between said second epitaxial region and said second doped region.

3. The transient voltage suppressor of claim 2 , wherein said semiconductor substrate is doped as said second doped type and a doped density is lighter than that of said second buried layer.

4. The transient voltage suppressor of claim 2 , wherein said conductive channel is configured as a doped region of said first doped type.

5. The transient voltage suppressor of claim 2 , wherein said first and second epitaxial regions are formed by a same epitaxial semiconductor layer by respectively auto-doping said first and second buried layers.

6. The transient voltage suppressor of claim 2 , further comprising a first isolation structure extending from a surface of said first and second epitaxial regions into said semiconductor substrate to isolate said transient voltage suppressor from adjacent semiconductor devices.

7. The transient voltage suppressor of claim 6 , further comprising a second isolation structure extending from a surface of said first and second epitaxial regions into said first buried layer to isolate said first and second epitaxial regions from said second buried layer.

8. The transient voltage suppressor of claim 6 , wherein said first isolation is configured to:
a) define a third region adjacent to said first region; and
b) a fourth region adjacent to said second region of said first buried layer, wherein said second epitaxial region is on said first buried layer in said third and fourth regions.

9. The transient voltage suppressor of claim 8 , wherein said third region comprises:
a) a third doped region of said first doped type in said second epitaxial region; and
b) a fourth doped region of said second doped type in said second epitaxial region, wherein said fourth region comprises a fifth doped region of said first doped type and a sixth doped region of said second doped type.

10. The transient voltage suppressor of claim 9 , wherein:
a) said first doped region and said fourth doped region are electrically connected by a first interconnection structure;
b) said second doped region and said fifth doped region are electrically connected by a second interconnection structure; and
c) said third doped region and said sixth doped region are electrically connected by a third interconnection structure.

11. The transient voltage suppressor of claim 9 , wherein said second region comprises a seventh doped region of said second doped type in said second doped region.

12. The transient voltage suppressor of claim 11 , wherein:
a) said first doped region and said fourth doped region are electrically connected by a first interconnection structure;
b) said seventh doped region and said fifth doped region are electrically connected by a second interconnection structure; and
c) said third doped region and said sixth doped region are electrically connected by a third interconnection structure.

13. The transient voltage suppressor of claim 6 , wherein:
a) said first isolation structure is configured to define adjacent third and fourth regions of said first buried layer, and said fourth region is adjacent to said first region;
b) in said third region, said second buried layer is on said first buried layer, and said first epitaxial region is on said second buried layer; and
c) in said fourth region, said second epitaxial region is on said first buried layer.

14. The transient voltage suppressor of claim 13 , wherein:
a) said third region comprises a third doped region of said first doped type in said first epitaxial region;
b) said fourth region comprises a fourth doped region of said second doped type in said second epitaxial region; and
c) said fourth region comprises another conductive channel extending from a surface of said second epitaxial region into said first buried layer.

15. The transient voltage suppressor of claim 14 , wherein said first, second, third, and fourth doped regions are electrically connected by said first interconnection structure.

16. The transient voltage suppressor of claim 1 , wherein said first doped type is one of N type and P type, and said second doped type is a remaining type of said N type and said P type.

17. A method of making a transient voltage suppressor, the method comprising:
a) forming a first buried layer in and on a semiconductor substrate;
b) forming a second buried layer of second doped type in a first region of said first buried layer to expose a surface of a second region of said first buried layer;
c) forming an epitaxial semiconductor layer on said first and second buried layers comprising a first epitaxial region connected to said second buried layer and a second epitaxial region connected to said first buried layer;
d) forming a conductive channel extending from a surface of said second epitaxial region into said first buried layer;
e) forming a first doped region of a first doped type in said first epitaxial region;
f) forming a second doped region of a second doped type in said second epitaxial region; and
g) forming a first electrode connected to said conductive channel, a second electrode connected to said doped region, and a third electrode connected to second doped region.

18. The method of claim 17 , further comprising forming a first isolation structure extending from a surface of said first and second epitaxial regions into said semiconductor substrate to isolate said transient voltage suppressor from adjacent semiconductor devices.

19. The method of claim 18 , further comprising forming a second isolation structure extending from a surface of said first and second epitaxial regions into said first buried layer to isolate said second epitaxial region from said first epitaxial region and said second buried layer.

20. The method of claim 18 , further comprising forming additional elements and interconnection structure, wherein said additional elements comprises at least two doped regions and at least two electrodes connected to said doped regions, and wherein said interconnection structure is configured to connect said first to third electrodes to at least portion of said at least two electrodes.

Assignees

• Silergy Semiconductor Technology Hangzhou Ltd

Inventors

• Yao Fei
• Wang Shijun

Classifications

• H10P14/40

  of conductive or resistive materials · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W10/031

  of isolation regions comprising PN junctions · CPC title

• H10W10/30

  Isolation regions comprising PN junctions · CPC title

• H01L29/0646

  Electricity · mapped topic