Semiconductor devices including conductive lines and methods of forming the semiconductor devices

Patent metadata

Field	Value
Publication number	US-9911693-B2
Application number	US-201514838768-A
Country	US
Kind code	B2
Filing date	Aug 28, 2015
Priority date	Aug 28, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A semiconductor device including conductive lines is disclosed. First conductive lines each comprise a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line. The semiconductor device includes second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof. The semiconductor device includes a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on the each of the first conductive lines is on the enlarged portion thereof.

First claim

What is claimed is:

1. A semiconductor device, comprising:
first conductive lines each comprising a first portion, a second portion, and an enlarged portion, the enlarged portion connecting the first portion and the second portion of the first conductive line;
second conductive lines, at least some of the second conductive lines disposed between a pair of the first conductive lines, each second conductive line including a larger cross-sectional area at an end portion of the second conductive line than at other portions thereof, wherein a number of the second conductive lines is equal to a number of the first conductive lines;
a pad on each of the first conductive lines and the second conductive lines, wherein the pad on each of the second conductive lines is on the end portion thereof and the pad on each of the first conductive lines is on the enlarged portion thereof; and
a conductive contact on the pad on the end portion of each second conductive line of the second conductive lines.

2. The semiconductor device of claim 1 , wherein the first portion and the second portion are laterally offset from one another.

3. The semiconductor device of claim 1 , wherein the end portions of the second conductive lines are located at a peripheral region of the semiconductor device.

4. The semiconductor device of claim 1 , wherein at least some of the enlarged portions comprise curved surfaces.

5. The semiconductor device of claim 1 , wherein the enlarged portions of the first conductive lines are located in an array region of the semiconductor device.

6. The semiconductor device of claim 1 , wherein the enlarged portions are longitudinally offset and laterally offset from one another.

7. The semiconductor device of claim 1 , wherein the first portion of the first conductive lines extends from a first end of the semiconductor device to the enlarged portion and the second portion of the first conductive lines extends from a second end of the semiconductor device to the enlarged portion and wherein the first portion is laterally offset from the second portion.

8. The semiconductor device of claim 1 , wherein the first conductive lines and the second conductive lines extend from a first end of the semiconductor device to a second end of the semiconductor device and are substantially coextensive in length.

9. The semiconductor device of claim 1 , wherein the first portion and the second portion of each first conductive line of the first conductive lines extend along a longitudinal axis of the respective first conductive line, the first portion and the second portion laterally offset from each other.

10. A semiconductor device, comprising:
conductive lines over a semiconductor substrate including memory cells, wherein:
every other of the conductive lines comprise first conductive lines including an enlarged portion located between end portions of the respective first conductive line, wherein the enlarged portion is wider than other portions of the respective first conductive line; and
other of the every other of the conductive lines comprise second conductive lines including an end portion having a larger cross-sectional area than other portions thereof;

a conductive contact on the enlarged portions of the first conductive lines; and
a conductive contact on the end portions of the second conductive lines, wherein the conductive contact of each second conductive line of the second conductive lines is laterally offset from a longitudinal axis of its respective second conductive line.

11. The semiconductor device of claim 10 , wherein the enlarged portions of the first conductive lines are between end portions of the first conductive lines.

12. The semiconductor device of claim 10 , further comprising pads at the end portions of the second conductive lines.

13. The semiconductor device of claim 12 , wherein the pads at the end portions comprise about one half of the pads of the conductive lines.

14. The semiconductor device of claim 10 , further comprising at least one opening at a peripheral region of the semiconductor device separating adjacent conductive lines.

15. The semiconductor device of claim 10 , further comprising a contact over each of the enlarged portions.

16. The semiconductor device of claim 10 , wherein adjacent conductive lines are separated by between about 10 nm and about 20 nm.

17. The semiconductor device of claim 10 , further comprising pads on the enlarged portions of the first conductive lines.

18. The semiconductor device of claim 10 , wherein the conductive contact of each second conductive line of the second conductive lines is disposed on the larger cross-sectional area of the end portion.

19. The semiconductor device of claim 10 , wherein the first conductive lines and the second conductive lines extend from one end of the semiconductor device to another end of the semiconductor device.

20. A semiconductor device, comprising:
conductive lines extending over memory cells of a semiconductor device, every other conductive line including an enlarged portion between end portions of the conductive line, the enlarged portion having a larger cross-sectional area than other portions of the conductive line and comprising at least one arcuate surface, the other of the every other conductive lines including an enlarged portion at an end portion thereof, about one half of the other of the every other conductive lines having the enlarged portion thereof at a first end of the conductive lines and about one half of the other of the every other conductive lines having the enlarged portion at a second end of the conductive lines.

21. The semiconductor device of claim 20 , further comprising contacts on the enlarged portion of the conductive lines.

22. The semiconductor device of claim 20 , wherein at least some of the conductive lines include an enlarged end portion.

23. The semiconductor device of claim 22 , further comprising contacts on the enlarged end portions of the conductive lines.

24. The semiconductor device of claim 22 , wherein the enlarged end portions are within the array region of the semiconductor device.

25. The semiconductor device of claim 20 , wherein the enlarged portions of the conductive lines are longitudinally offset from one another.

26. A method of forming a semiconductor device, the method comprising:
forming conductive lines over a semiconductor device, forming the conductive lines comprising:
forming first conductive lines to have a first portion and a second portion connected to the first portion by an enlarged portion;
forming second conductive lines between a pair of the first conductive lines, the second conductive lines including a larger cross-sectional area at an end portion thereof than at other portions thereof, wherein forming the conductive lines comprises forming a number of the second conductive lines to be equal to a number of the first conductive lines;
forming a pad on each of the first conductive lines on the enlarged portion thereof; and
forming a pad on each of the second conductive lines on the end portion thereof; and

forming a conductive contact on the pad on the end portion of each second conductive line of the second conductive lines.

27. The method of claim 26 , further comprising forming the enlarged portions of at least some of the first conductive lines to have larger cross-sectional areas than other portions of the c

Assignees

• Micron Technology Inc

Inventors

• Brown William R
• Russon Jenna L
• Bossart Tim H
• Watson Brian R
• Mirin Nikolay A
• Kewley David A

Classifications

• H10W20/0633

  using subtractive patterning of the conductive members · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• H10P74/273

  Interconnections for measuring or testing, e.g. probe pads · CPC title

• H10P74/27

  Structural arrangements therefor · CPC title

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title