Self aligned conductive lines

Patent metadata

Field	Value
Publication number	US-9911647-B2
Application number	US-201715677447-A
Country	US
Kind code	B2
Filing date	Aug 15, 2017
Priority date	Jun 8, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A method for forming conductive lines on a wafer comprises forming a first hardmask, a planarizing layer, a second hardmask, a layer of sacrificial mandrel material on the second hardmask, and patterning a mask on the layer of sacrificial material. A first sacrificial mandrel and a second sacrificial mandrel and a gap are formed. A layer of spacer material is deposited in the gap. Portions of the first sacrificial mandrel and the second sacrificial mandrel are removed, and exposed portions of the second hardmask, the planarizing layer and the first hardmask are removed to expose portions of the insulator layer. The second hardmask, the spacers, and the planarizing layer are removed. Exposed portions of the insulator layer are removed to form a trench in the insulator layer, and the trench is filled with a conductive material.

First claim

What is claimed is:

1. A method for forming conductive lines on a semiconductor wafer, the method comprising:
forming a first hardmask on an insulator layer, a planarizing layer on the first hardmask, a second hardmask on the planarizing layer and a layer of sacrificial mandrel material on the second hardmask;
patterning a mask on the layer of sacrificial material;
removing exposed portions of the layer of sacrificial mandrel material to expose portions of the second hardmask and form a first sacrificial mandrel and a second sacrificial mandrel on the second hardmask, wherein the first sacrificial mandrel has a gap defined by a first portion of the first sacrificial mandrel and a second portion of the first sacrificial mandrel;
depositing a layer of spacer material in the gap, and over exposed portions of the first sacrificial mandrel, the second sacrificial mandrel and the second hardmask;
depositing a filler material on the layer of spacer material;
removing portions of the layer of spacer material and the filler material to expose portions of the first sacrificial mandrel and the second sacrificial mandrel;
removing the filler material;
depositing a second filler material on the layer of spacer material;
patterning a mask over a portion of the second filler material;
removing exposed portions of the second filler material;
removing the second filler material, the first sacrificial mandrel and the second sacrificial mandrel to expose portions of the second hardmask;
removing exposed portions of the second hardmask, the planarizing layer and the first hardmask to expose portions of the insulator layer;
removing the second hardmask, the spacers, and the planarizing layer;
removing exposed portions of the insulator layer to form a trench in the insulator layer; and
filling the trench with a conductive material.

2. The method of claim 1 , wherein the method further comprises depositing a liner layer in the trench prior to depositing the conductive material.

3. The method of claim 1 , wherein the trench defines a conductive line.

4. The method of claim 1 , wherein the sacrificial mandrel material, the spacers and the filler material are dissimilar materials.

5. The method of claim 1 , wherein the spacers are formed from an oxide material.

6. The method of claim 1 , wherein the layer of sacrificial mandrel material includes a semiconductor material.

7. The method of claim 1 , wherein the filler material includes a flowable carbide material.

8. The method of claim 1 , wherein the sacrificial mandrel material includes an amorphous silicon material.

9. The method of claim 8 , wherein the first hardmask includes titanium nitride.

10. The method of claim 9 , wherein each of the first hardmask and the second hardmask include a same material.

11. The method of claim 9 , wherein the first hardmask and the second hardmask include dissimilar materials.

12. A method for forming conductive lines on a semiconductor wafer, the method comprising:
forming a first hardmask on an insulator layer, a planarizing layer on the first hardmask, a second hardmask on the planarizing layer;
patterning a mask on the second hardmask;
removing exposed portions of the second hardmask to expose portions of the planarizing layer;
forming a third hardmask over the second hardmask and exposed portions of the planarizing layer;
forming a layer of sacrificial mandrel material over the third hardmask;
forming a fourth hardmask on the layer of sacrificial mandrel material;
removing a portion of the fourth hardmask to expose a portion of the layer of sacrificial mandrel material;
patterning a mask on portions of the fourth hardmask and the layer of sacrificial mandrel material;
removing exposed portions of the fourth hardmask to expose portions of the layer of sacrificial mandrel material;
removing exposed portions of the layer of sacrificial mandrel material to expose portions of the third hardmask and form a first sacrificial mandrel and a second sacrificial mandrel on the third hardmask, wherein the first sacrificial mandrel has a gap defined by a first portion of the first sacrificial mandrel and a second portion of the first sacrificial mandrel;
depositing a layer of spacer material in the gap, and over exposed portions of the first sacrificial mandrel, the second sacrificial mandrel, the third hardmask, and the second hardmask;
removing portions of the layer of spacer material to expose portions of the first sacrificial mandrel and the second sacrificial mandrel and form spacers adjacent to the first sacrificial mandrel and the second sacrificial mandrel;
depositing a filler material over the layer of spacer material, the first sacrificial mandrel, and the second sacrificial mandrel;
removing portions of the filler material to expose portions of the first sacrificial mandrel and the second sacrificial mandrel;
removing the first sacrificial mandrel and the second sacrificial mandrel;
removing exposed portions of the third hardmask and the second hardmask;
removing exposed portions of the planarizing layer to expose portions of the first hardmask;
removing the layer of spacer material;
removing exposed portions of the first hardmask to expose portions of the insulator material;
removing the second hardmask and the planarizing layer;
removing exposed portions of the insulator layer to form a trench in the insulator layer; and
filling the trench with a conductive material.

13. The method of claim 12 , wherein the method further comprises depositing a liner layer in the trench prior to depositing the conductive material.

14. The method of claim 12 , wherein the trench defines a conductive line.

15. The method of claim 12 , wherein the sacrificial mandrel material, the spacers and the filler material are dissimilar materials.

16. The method of claim 12 , wherein the spacers are formed from an oxide material.

17. The method of claim 12 , wherein the layer of sacrificial mandrel material includes a semiconductor material.

18. The method of claim 12 , wherein the sacrificial mandrel material includes an amorphous silicon material.

19. The method of claim 18 , wherein the first hardmask includes titanium nitride.

20. The method of claim 19 , wherein each of the first hardmask and the second hardmask include a same material.

Assignees

• IBM

Inventors

• Burns Sean D
• Clevenger Lawrence A
• Desilva Anuja E
• Felix Nelson M
• Kanakasabapathy Sivananda K
• Mignot Yann A M
• Penny Christopher J
• Quon Roger A
• Saulnier Nicole A

Classifications

• H10P76/4085

  characterised by the processes involved to create the masks · CPC title

• H10P50/73

  using masks for insulating materials · CPC title

• H10W20/069

  by forming self-aligned vias or self-aligned contact plugs · CPC title

• H10W20/43

  Layouts of interconnections · CPC title

• H10W20/089 Primary

  using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning · CPC title