Low temperature poly-silicon thin film transistor, fabricating method thereof, array substrate and display device

Patent metadata

Field	Value
Publication number	US-9911618-B2
Application number	US-201615085217-A
Country	US
Kind code	B2
Filing date	Mar 30, 2016
Priority date	May 5, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Embodiments of the present invention disclose a low temperature poly-silicon thin film transistor and a method of fabricating the same, an array substrate, and a display device. The low temperature poly-silicon thin film transistor comprises an active layer, a source and a drain, wherein the active layer comprises a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region, the source is provided above and connected to the source contact region, the drain being provided above and connected to the drain contact region, and thicknesses of the source contact region and the drain contact region are both larger than that of the channel region.

First claim

What is claimed is:

1. A low temperature poly-silicon thin film transistor, comprising an active layer, a source and a drain, a gate provided above the active layer; and a gate insulating layer provided between the gate and the active layer, wherein
the active layer comprises a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region,
the source is provided above and connected to the source contact region, and the drain is provided above and connected to the drain contact region,
thicknesses of the source contact region and the drain contact region are both larger than that of the channel region,
the gate insulating layer comprises a silicon oxide layer provided on the active layer and contacting the active layer and a silicon nitride layer provided on a side of the silicon oxide layer distal to the active layer, and
a groove is formed on a surface of the source contact region contacting the source, and a groove is formed on a surface of the drain contact region contacting the drain.

2. The low temperature poly-silicon thin film transistor of claim 1 , wherein an ohmic contact layer is provided between the source contact region and the source and between the drain contact region and the drain.

3. The low temperature poly-silicon thin film transistor of claim 1 , wherein the thickness of the source contact region is the same as that of the drain contact region.

4. The low temperature poly-silicon thin film transistor of claim 1 , further comprising:
an interlayer insulating layer provided on the gate; and
a source via hole and a drain via hole each penetrating through the gate insulating layer and the interlayer insulating layer, wherein the source is connected to the source contact region through the source via hole, and the drain is connected to the drain contact region through the drain via hole.

5. The low temperature poly-silicon thin film transistor of claim 4 , wherein the interlayer insulating layer comprises a silicon oxide layer provided on the gate and a silicon nitride layer provided on the silicon oxide layer.

6. An array substrate, comprising the low temperature poly-silicon thin film transistor of claim 1 .

7. A display device, comprising the array substrate of claim 6 .

8. A method for fabricating a low temperature poly-silicon thin film transistor, comprising:
forming an active layer, wherein the active layer comprises a source contact region, a drain contact region, and a channel region located between the source contact region and the drain contact region, and thicknesses of the source contact region and the drain contact region are both larger than that of the channel region; and
forming a source and a drain above the source contact region and the drain contact region, respectively, so that the source is connected to the source contact region and the drain is connected to the drain contact region,
wherein the method further comprises forming a gate insulating layer on the active layer; and forming a gate on the gate insulating layer, wherein the gate insulating layer comprises a silicon oxide layer formed on the active layer and contacting the active layer and a silicon nitride layer formed on a side of the silicon oxide layer distal to the active layer, and
wherein a groove is formed on a surface of the source contact region contacting the source, and a groove is formed on a surface of the drain contact region contacting the drain.

9. The method of claim 8 , wherein forming the active layer comprises:
forming a first amorphous silicon material layer;
forming a photoresist layer on the first amorphous silicon material layer, and performing a patterning process to maintain portions of the first amorphous silicon material layer located in a first region and a second region with other portions being removed, so as to form a first intermediate pattern, wherein the first region corresponds to a position where the source contact region is located, and the second region corresponds to a position where the drain contact region is located;
forming a second amorphous silicon material layer;
forming a photoresist layer on the second amorphous silicon material layer, and performing a patterning process to maintain portions of the second amorphous silicon material layer located in the first region, the second region and a third region with other portions being removed, so as to form a second intermediate pattern, wherein the third region corresponds to a position where the channel region is located; and
performing annealing on the first intermediate pattern and second intermediate pattern, so as to form the active layer.

10. The method of claim 9 , wherein an excimer laser annealing process is adopted to perform annealing on the first intermediate pattern and the second intermediate pattern.

11. The method of claim 10 , wherein poly-silicon laterally grows in the channel region having a smaller thickness, so as to form poly-silicon with a large grain size in the channel region.

12. The method of claim 10 , wherein before forming the active layer, the method further comprises forming a buffer layer on a substrate.

13. The method of claim 8 , further comprising:
performing ion doping on the source contact region and the drain contact region to form an ohmic contact layer.

14. The method of claim 8 , further comprising:
forming an interlayer insulating layer on the gate; and
forming a source via hole penetrating through both the gate insulating layer and the interlayer insulating layer at a position corresponding to the source contact region, and forming a drain via hole penetrating through both the gate insulating layer and the interlayer insulating layer at a position corresponding to the drain contact region.

15. The method of claim 14 , wherein the source is connected to the source contact region through the source via hole, and the drain is connected to the drain contact region through the drain via hole.

16. The method of claim 14 , wherein forming the interlayer insulating layer comprises: sequentially forming a silicon oxide layer and a silicon nitride layer on the gate.

Assignees

• Boe Technology Group Co Ltd
• Chengdu Boe Optoelect Tech Co

Inventors

• Li Xinghua
• Bao Junping

Classifications

• H10P50/642

  Chemical etching · CPC title

• H10P50/694 Primary

  characterised by their behaviour during the process, e.g. soluble masks or redeposited masks · CPC title

• G02F1/1362

  Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} · CPC title

• H01L29/41783

  Electricity · mapped topic

• H01L29/78675

  Electricity · mapped topic