Resistance variable memory apparatus and operating method thereof

Patent metadata

Field	Value
Publication number	US-9911467-B2
Application number	US-201615275732-A
Country	US
Kind code	B2
Filing date	Sep 26, 2016
Priority date	May 24, 2016
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A resistance variable memory apparatus may include a memory cell array and a controller. The memory cell array may include a plurality of resistance variable memory cells. The controller may control a current path flowing through any one memory cell and a current path flowing through the other memory cell to be formed differently from each other in response to at least two address signals.

First claim

What is claimed is:

1. A resistance variable memory apparatus comprising:
a memory cell array including a plurality of resistance variable memory cells;
a controller configured to simultaneously control a current path flowing through any one memory cell and a current path flowing through the other memory cell to be formed differently from each other in response to at least two address signals,
wherein the controller is configured to control so that a program voltage is applied to a selected word line in a test program mode,
wherein the address signals have different column addresses and different row addresses from each other;
a row-side write control circuit including a first write driver and a first current sink circuit, wherein the row-side control circuit is coupled to a plurality of word lines; and
a read/write circuit configured to include a second write driver and a second current sink circuit, wherein the read/write circuit is coupled to a plurality of bit lines.

2. The resistance variable memory apparatus of claim 1 , wherein the at least two address signals are provided in the test program mode.

3. The resistance variable memory apparatus of claim 1 , wherein the controller controls a current to flow from a first bit line toward a first word line to program the one memory cell coupled between the first bit line and the first word line, and controls a current to flow from a second word line toward a second bit line to program the other memory cell coupled between the second bit line and the second word line.

4. A resistance variable memory apparatus comprising:
a memory cell array including a plurality of resistance variable memory cells coupled between a plurality of word lines and a plurality of bit lines;
a row-side write control circuit including a first write driver and a first current sink circuit, wherein the first write driver is configured to provide a program voltage to a selected word line in a test program mode;
a first switching circuit configured to control a connection path between the row-side write control circuit and the plurality of word lines;
a read/write circuit configured to include a second write driver and a second current sink circuit;
a second switching circuit configured to control an electrical connection path between the read/write circuit and the plurality of bit lines; and
a controller configured to simultaneously control the first switching circuit and the second switching circuit to control an electrical connection path between the row-side write control circuit and the read/write circuit via a plurality of memory cells corresponding to a plurality of address signals in response to the plurality of address signals;
wherein the address signals include different column addresses and different row addresses from each other.

5. The resistance variable memory apparatus of claim 4 , wherein the address signals are provided in the test program mode.

6. The resistance variable memory apparatus of claim 4 , wherein the controller is configured to control a current path flowing through a memory cell corresponding to any one of the plurality of address signals and a current path flowing through a memory cell corresponding to the other of the plurality of address signals to be formed differently from each other.

7. The resistance variable memory apparatus of claim 4 , wherein the controller is configured to control a bit line of a first memory cell corresponding to any one of the plurality of address signals to be coupled to the second write driver and control a word line of the first memory cell to be coupled to the first current sink circuit, and to control a bit line of a second memory cell corresponding to the other of the plurality of address signals to be coupled to the second current sink circuit and control a word line of the second memory cell to be coupled to the first write driver.

Assignees

• Sk Hynix Inc

Inventors

• Cheon Jun Ho

Classifications

• G11C7/1006 Primary

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C7/1045

  Read-write mode select circuits · CPC title

• G11C13/00

  Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 · CPC title

• G11C2029/2602

  Concurrent test · CPC title

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title