Overlapping, discrete tamper-respondent sensors

Patent metadata

Field	Value
Publication number	US-9911012-B2
Application number	US-201514865572-A
Country	US
Kind code	B2
Filing date	Sep 25, 2015
Priority date	Sep 25, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

Tamper-respondent assemblies, electronic assembly packages, and methods of fabrication are provided which include multiple, discrete tamper-respondent sensors that overlap, at least in part, and facilitate defining a secure volume about one or more electronic components to be protected, such as an electronic assembly. The tamper-respondent sensors include a first tamper-respondent sensor and a second tamper-respondent sensor, which may be similarly constructed or differently constructed. In certain embodiments, the tamper-respondent sensors wrap, at least in part, over an electronic enclosure, and in other embodiments, the tamper-respondent sensors cover, at least in part, an inner surface of an electronic enclosure to facilitate defining a secure volume in association with a multilayer circuit board to which the electronic enclosure is mounted.

First claim

What is claimed is:

1. A tamper-respondent assembly comprising:
a first tamper-respondent sensor, the first tamper-respondent sensor comprising:
at least one first formed flexible layer having opposite first and second sides with surface curvatures extending from the opposite first and second sides of the at least one first formed flexible layer;
first circuit lines forming at least one first resistive network, the first circuit lines being disposed on at least one of the first side or the second side of the at least one first layer, the first circuit lines wrapping over or within the surface curvatures extending from the at least one of the first side or second side of the at least one first layer;

a second tamper-respondent sensor, the second tamper-respondent sensor comprising:
at least one second formed flexible layer having opposite first and second sides with surface curvatures extending from the opposite first and second sides of the at least one second formed flexible layer;
second circuit lines forming at last one second resistive network, the second circuit lines being disposed on at least one of the first side or the second side of the at least one second layer, the second circuit lines wrapping over or within the surface curvatures extending from the at least one of the first side or second side of the at least one second layer; and

the first tamper-respondent sensor and the second tamper-respondent sensor being discrete, tamper-respondent sensors that overlap, at least in part, and facilitate defining a secure volume about at least one electronic component to be protected.

2. The tamper-respondent assembly of claim 1 , wherein the first tamper-respondent sensor and the second tamper-respondent sensor are positioned, at least in part, about an electronic enclosure to be protected, the electronic enclosure comprising the at least one electronic component.

3. The tamper-respondent assembly of claim 2 , wherein the first tamper-respondent sensor comprises one of an upper tamper-respondent sensor or lower tamper-respondent sensor disposed over a respective upper or lower exterior surface of the electronic enclosure, and wherein the second tamper-respondent sensor comprises an outer sidewall tamper-respondent sensor wrapping around an exterior periphery of the electronic enclosure.

4. The tamper-respondent assembly of claim 1 , wherein the first tamper-respondent sensor and second tamper-respondent sensor are associated with an electronic enclosure, the electronic enclosure mounting to a multilayer circuit board comprising at least one electronic component to be protected, wherein the first tamper-respondent sensor and second tamper-respondent sensor cover, at least in part, an inner surface of the electronic enclosure and facilitate defining a secure volume between the enclosure and the multilayer circuit board.

5. The tamper-respondent assembly of claim 4 , further comprising an embedded tamper-respondent sensor within the multilayer circuit board, the first tamper-respondent sensor, second tamper-respondent sensor, and embedded tamper-respondent sensor together defining the secure volume therebetween.

6. The tamper-respondent assembly of claim 5 , wherein the first tamper-respondent sensor and the second tamper-respondent sensor cover and are adhesively secured to the inner surface of the electronic enclosure.

7. The tamper-respondent assembly of claim 5 , wherein the second tamper-respondent sensor comprises an inner sidewall tamper-respondent sensor disposed over an inner sidewall of the electronic enclosure, and the first tamper-respondent sensor comprises a main surface tamper-respondent sensor disposed over a main inner surface of the electronic enclosure, and wherein the first tamper-respondent sensor overlaps, at least in part, the second tamper-respondent sensor.

8. A tamper-respondent assembly comprising:
a first tamper-respondent sensor, the first tamper-respondent sensor comprising:
at least one first layer having opposite first and second sides;
first circuit lines forming at least one first resistive network, the first circuit lines being disposed on at least one of the first side or the second side of the at least one first layer;

a second tamper-respondent sensor, the second tamper-respondent sensor comprising:
at least one second layer having opposite first and second sides;
second circuit lines forming at least one second resistive network, the second circuit lines being disposed on at least one of the first side or the second side of the at least one second layer; and

the first tamper-respondent sensor and the second tamper-respondent sensor being discrete, tamper-respondent sensors that overlap, at least in part, and facilitate defining a secure volume about at least one electronic component to be protected;
wherein the first tamper-respondent sensor and the second tamper-respondent sensor are interweaved and define a multi-sensor interweaved layer; and
wherein the first tamper-respondent sensor comprises multiple first slits therein, and the second tamper-respondent sensor comprises multiple second slits therein, the multiple first slits and the multiple second slits facilitating the interweaving of the first tamper-respondent sensor and the second tamper-respondent sensor to define the multi-sensor interweaved layer.

9. A tamper-respondent assembly comprising:
a first tamper-respondent sensor, the first tamper-respondent sensor comprising:
at least one first layer having opposite first and second sides;
first circuit lines forming at least one first resistive network, the first circuit lines being disposed on at least one of the first side or the second side of the at least one first layer;

a second tamper-respondent sensor, the second tamper-respondent sensor comprising:
at least one second layer having opposite first and second sides;
second circuit lines forming at least one second resistive network, the second circuit lines being disposed on at least one of the first side or the second side of the at least one second layer; and

the first tamper-respondent sensor and the second tamper-respondent sensor being discrete, tamper-respondent sensors that overlap, at least in part, and facilitate defining a secure volume about at least one electronic component to be protected;
wherein the first tamper-respondent sensor and the second tamper-respondent sensor are interweaved and define a multi-sensor interweaved layer; and
wherein the multi-sensor interweaved layer is a first multi-sensor interweaved layer, and wherein the tamper-respondent electronic circuit structure further comprises a second multi-sensor interweaved layer overlying the first multi-sensor interweaved layer, the second multi-sensor interweaved layer comprising additional discrete tamper-respondent sensors.

Assignees

• IBM

Inventors

• Brodsky William L
• Dangler John R
• Isaacs Phillip Duane
• Long David C
• Peets Michael T

Classifications

• H10W42/405

  using active circuits · CPC title

• H05K2201/055

  Folded back on itself · CPC title

• G06F21/87 Primary

  by means of encapsulation, e.g. for integrated circuits · CPC title

• G06F21/75

  by inhibiting the analysis of circuitry or operation · CPC title

• H05K5/03

  Covers · CPC title