Two-wire serial interface and protocol

Patent metadata

Field	Value
Publication number	US-9910819-B2
Application number	US-201414197330-A
Country	US
Kind code	B2
Filing date	Mar 5, 2014
Priority date	Mar 11, 2013
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

In a serial transmission method using a two-wire serial interface, a master device transmits a first synchronous serial signal via the two-wire serial interface to wake-up a slave device followed by an asynchronous data transmission on one of the two-wires of the two-wire serial interface. The asynchronous data signal directly controls a function of the slave device.

First claim

What is claimed is:

1. A serial transmission method using a two-wire serial interface, comprising:
coupling a master device with a slave device through the two-wire serial interface, wherein the slave device comprises a first and second external pin coupled with an interface control unit configured to decode signals transmitted through the two-wire serial interface and an analog functional unit having a modulator input generating an output signal on a third external pin of the slave device; and performing the steps of:
operating the two-wire serial interface as a synchronous serial interface, wherein a first wire is operated as a data signal wire and a second wire as a clock signal wire;
transmitting by the master device a first synchronous serial signal via said two-wire serial interface, wherein the interface control unit of the slave device receives the first synchronous serial signal and is configured to wake-up the slave device and to directly connect one of the first or second wire with the functional unit; and
thereafter transmitting by the master device an asynchronous data signal on the one of the first or the second wire of the two-wire serial interface, wherein the logic states of the asynchronous data signal directly modulate an analog output signal at the third external pin of the slave device.

2. The method according to claim 1 , wherein the synchronous serial signal comprises configuration data for the slave device and wherein the interface control unit of the slave device decodes said configuration data.

3. The method according to claim 1 , wherein the synchronous serial signal comprises a calibration request and wherein the interface control unit of the slave device decodes said calibration request.

4. The method according to claim 1 , wherein the slave device comprises a radio frequency transmitter.

5. The method according to claim 4 , wherein the functional unit is an on-off-key (OOK) radio frequency transmitter.

6. The method according to claim 5 , wherein the asynchronous data signal turns the transmitter on or off, respectively according to its logic state.

7. The method according to claim 1 , wherein a communication via said two-wire serial interface comprises a start pattern followed by an asynchronous data transmission followed by a stop pattern.

8. The method according to claim 7 , wherein the communication further comprises a wake-up wait period.

9. The method according to claim 7 , wherein the communication further comprises a configuration bit within said synchronous signal.

10. The method according to claim 9 , wherein when said configuration bit is set the communication comprises synchronous configuration data.

11. The method according to claim 7 , wherein the communication further comprises a calibration bit within said synchronous signal.

12. The method according to claim 11 , wherein when said calibration bit is set the slave device will perform a calibration.

13. A system comprising a master device and a slave device coupled through a two-wire serial interface comprising a signal line and a clock line coupled first and second external pins of the slave device, wherein the master device is configured to control the slave device by controlling the two-wire serial interface to operate in a synchronous mode and to transmit a synchronous serial data signal via said two-wire serial interface to wake-up the slave device, wherein the slave device comprises a switch which after waking up the slave device is controlled to couple the one of the two-wires of the two-wire serial interface with an input of a modulator wherein the logic states of a data signal on the one of the two-wires of the two-wire serial interface directly modulates an analog function of the slave device.

14. The system according to claim 13 , wherein the slave device is an on-off-key (OOK) radio frequency transmitter coupled with a third external pin of the slave device, wherein the data signal on the one of the two-wires of the two-wire serial interface turns the transmitter on or off, respectively according to its logic state.

15. The system according to claim 13 , wherein a communication via said two-wire serial interface comprises a start pattern followed by a data transmission on the one of the two-wires of the two-wire serial interface followed by a stop pattern.

16. The system according to claim 13 , wherein the communication further comprises a wake-up wait period.

17. The system according to claim 13 , wherein the communication further comprises a configuration bit within said synchronous signal.

18. The system according to claim 17 , wherein when said configuration bit is set the communication comprises synchronous configuration data.

19. The system according to claim 13 , wherein the communication further comprises a calibration bit within said synchronous signal.

20. The system according to claim 19 , wherein when said calibration bit is set the slave device will perform a calibration.

21. An integrated circuit device comprising:
a two wire serial interface coupled with a first and a second external pin of the integrated circuit device,
a switch coupled with the first external pin,
a control unit coupled with said two-wire serial interface and configured to decode synchronous transmission data and to control said switch, and
a functional unit coupled with said switch and with a third external pin of the integrated circuit device and being controlled by the control unit, wherein the control unit is operable to receive a first synchronous serial signal via said two-wire serial interface to wake-up the integrated circuit device and thereafter to control the switch to couple the first external pin with the functional unit, wherein the logic states of a data signal at the first pin directly control the functional unit of the integrated circuit device, wherein an analog signal which is directly modulated by said data signal is output at the third external pin.

22. The integrated circuit device according to claim 21 , wherein the integrated circuit device is an on-off-key (OOK) radio frequency transmitter, wherein the data signal at the first pin turns the transmitter on or off, respectively according to its logic state.

23. The integrated circuit device according to claim 21 , wherein a communication received via said two-wire serial interface comprises a start pattern followed by said data signal followed by a stop pattern.

24. The integrated circuit device according to claim 21 , wherein the communication further comprises a wake-up wait period during which the operational units of integrated circuit device are woken up from a sleep mode by said control unit.

25. The integrated circuit device according to claim 21 , wherein the communication further comprises a configuration bit within said synchronous signal.

26. The integrated circuit device according to claim 25 , wherein when said configuration bit is set the communication comprises synchronous configuration data.

27. The integrated circuit device according to claim 21 , wherein the communication further comprises a calibration bit within said synchronous signal.

28. The integrated circuit device according to claim 27 , wherein when said calibration bit is set the integrated circuit device will perform a calibration.

29. The integrated circuit device according to claim 21 , wherein the

Assignees

• Microchip Tech Inc

Inventors

• Erdelyi Janos
• Bible Steven
• Li Phil
• Kovacs Peter

Classifications

• G06F13/4295 Primary

  using an embedded synchronisation · CPC title

• G06F13/4291

  using a clocked protocol · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title