Multi master arbitration scheme in a system on chip

Patent metadata

Field	Value
Publication number	US-9910803-B2
Application number	US-201414306970-A
Country	US
Kind code	B2
Filing date	Jun 17, 2014
Priority date	Jun 17, 2013
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A multi master system on chip (SoC) includes a plurality of masters comprising a first master and a second master, each configured to generate a request. A next state generator in the multi master SoC is configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer. The round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer. Further, the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

First claim

What is claimed is:

1. A multi-master system on chip, comprising:
a plurality of masters comprising a first master and a second master, each of the plurality of masters configured to generate a request; and
a next state generator configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer;
wherein the round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer, and wherein the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

2. The multi-master system on chip of claim 1 , wherein the next state generator comprises:
a multiplexer configured to generate the next state of the round robin pointer in response to the current state of the round robin pointer and only pending requests from the second master.

3. The multi-master system on chip of claim 1 , wherein each master comprises a plurality of ports that are configured to generate the request that includes a read request and a write request.

4. The multi-master system on chip of claim 1 , wherein the next state and the current state of the round robin pointer are configured to be independent of the number of requests from each master.

5. The multi-master system on chip of claim 1 , wherein the next state and the current state of the round robin pointer are configured to be determined by the plurality of masters in the multi-master system on chip.

6. The multi-master system on chip of claim 1 and further comprising:
a plurality of priority encoders, each associated with the one of the plurality of masters, configured to generate a grant signal to the associated master that completes the request.

7. The multi-master system on chip of claim 6 , wherein the each of the plurality of priority encoders is configured to generate the grant signal using a fixed priority arbitration scheme in response to the enable signal and the requests from each port of a same master.

8. The multi-master system on chip of claim 6 , wherein one of the plurality of encoders is configured to be enabled in a given state of the round robin pointer.

9. The multi-master system on chip of claim 1 , wherein the round robin pointer is configured to be in a same state until there is a request from the second master.

10. The multi-master system on chip of claim 1 , wherein requests from different masters of the plurality of masters are configured to be arbitrated using round robin arbitration scheme and requests from a same master are configured to be arbitrated with fixed priority arbitration scheme.

11. A method for arbitrating in a multi-master system on chip, the method comprising:
generating a request from a plurality of masters comprising a first master and a second master;
generating a next state of a round robin pointer in response to the request and a current state of the round robin pointer; and
generating an enable signal to enable a priority encoder for the first master in response to the next state of the round robin pointer, such that priority for the first master is maintained until there is a request from the second master.

12. The method of claim 11 , wherein the next state and the current state of the round robin pointer are configured to be independent of the number of requests from each master.

13. The method of claim 11 , wherein the next state and the current state of the round robin pointer are determined by the plurality of masters in the multi-master system on chip.

14. A multi-master system on chip, comprising:
a plurality of masters comprising a first master and a second master, each of the plurality of masters configured to generate a request;
a next state generator having a multiplexer configured to generate a next state of a round robin pointer in response to the request and a current state of the round robin pointer; and
a plurality of priority encoders, each associated with the plurality of masters configured to generate a grant signal to the associated master that completes the request; wherein:
the round robin pointer is configured to generate an enable signal to enable a priority encoder for the first master in response to the current state of the round robin pointer; and
the next state of the round robin pointer is generated such that a priority is maintained for the first master until there is a request from the second master.

15. The multi-master system on chip of claim 14 , wherein the next state and the current state of the round robin pointer are configured to be independent of the number of requests from each master.

16. The multi-master system on chip of claim 14 , wherein the next state and the current state of the round robin pointer are determined by the plurality of masters in the multi-master system on chip.

17. The multi-master system on chip of claim 14 , wherein the each of the plurality of priority encoders is configured to generate the grant signal using a fixed priority arbitration scheme in response to the enable signal and the requests from each port of a same master.

18. The multi-master system on chip of claim 14 , wherein one of the plurality of encoders is configured to be enabled in a given state of the round robin pointer.

19. The multi-master system on chip of claim 14 , wherein the round robin pointer is configured to be in a same state until there is a request from the second master.

Assignees

• Texas Instruments Inc

Inventors

• Langadi Saya Goud

Classifications

• G06F13/37 Primary

  using a physical-position-dependent priority, e.g. daisy chain, round robin or token passing · CPC title

• G06F13/1657

  Access to multiple memories · CPC title