Performing power management in a multicore processor

Patent metadata

Field	Value
Publication number	US-9910481-B2
Application number	US-201514621731-A
Country	US
Kind code	B2
Filing date	Feb 13, 2015
Priority date	Feb 13, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

In an embodiment, a processor a plurality of cores to independently execute instructions, the cores including a plurality of counters to store performance information, and a power controller coupled to the plurality of cores, the power controller having a logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores to independently execute instructions, each of the plurality of cores including a plurality of counters to store performance information; and
a power controller coupled to the plurality of cores, the power controller including:
a machine learning logic to receive performance information from at least some of the plurality of counters, determine a number of cores to be active and a performance state for the number of cores for a next operation interval, based at least in part on the performance information and model information comprising training information obtained offline during a machine learning training and stored in a storage of the processor during manufacture of the processor, and cause the number of cores to be active during the next operation interval, the performance information associated with execution of a workload on one or more of the plurality of cores.

2. The processor of claim 1 , further comprising a configuration storage including a plurality of entries each to store a number of cores to be enabled and one or more pairs of voltage/frequency at which the number of cores are to operate.

3. The processor of claim 2 , wherein the machine learning logic is coupled to the configuration storage to access one or more of the plurality of entries and determine the number of cores to be active for the next operation interval based at least in part thereon.

4. The processor of claim 1 , wherein the machine learning logic is to classify a workload based at least in part on the performance information and determine the number of cores to be active for the next operation interval based on the workload classification.

5. The processor of claim 4 , wherein if the workload classification indicates a memory bound workload, the logic is to determine the number of cores to be active for the next operation interval to be less than a current number of active cores.

6. The processor of claim 4 , wherein if the workload classification indicates a memory bound workload, the logic is to cause one or more threads to be migrated from a first type of core to a second type of core for the next operation interval.

7. The processor of claim 1 , wherein the machine learning logic comprises a heuristic logic, and the model information is to be obtained from a heuristic storage of the processor to store power configuration information associated with the workload.

8. The processor of claim 1 , wherein the machine learning logic includes an update logic to update at least some of the training information based on a history of operation of the processor and one or more configuration predictions by the machine learning logic during a lifetime of the processor.

9. The processor of claim 1 , wherein the machine learning logic includes a history logic to receive a prediction of the number of cores to be active in the next operation interval and to enable the logic to cause the number of cores to be active in the next operation interval based on a history of prior predictions.

10. The processor of claim 9 , wherein the history logic comprises a counter to maintain a count of a number of consecutive predictions for a first number of cores to be active in the next operation interval, wherein the history logic is to enable the logic to cause the first number of cores to be active in the next operation interval when the count exceeds a threshold, and otherwise to not enable the first number of cores to be active in the next operation interval.

11. The processor of claim 1 , wherein the machine learning logic is to maintain a current number of active cores for the next operation interval if a performance impact of execution of the workload on the determined number of cores would exceed a threshold level.

12. A system comprising:
a processor including:
a plurality of cores to independently execute instructions; and
a power controller coupled to the plurality of cores to:
receive workload characteristic information of a workload executed on a first number of active cores in a first operation interval, configuration information regarding the first number of active cores, and power state information of the first number of active cores;
obtain trained model parameter information from a storage of the processor based at least in part on the workload characteristic information;
classify the workload based on the workload characteristic information, the configuration information, and the power state information, including to generate a power configuration prediction from the trained model parameter information; and
schedule one or more threads to a different number of active cores for a next operation interval based at least in part on the workload classification having the power configuration prediction, and update a power state of one or more of the plurality of cores to enable the different number of active cores for the next operation interval; and

a dynamic random access memory (DRAM) coupled to the processor.

13. The system of claim 12 , wherein the power controller is to generate the power configuration prediction having a reduced number of active cores for the next operation interval if the workload is classified as a memory bounded workload.

14. The system of claim 13 , wherein the power controller is to determine whether the power configuration prediction is consistent with history information, and if so schedule the one or more threads to the reduced number of active cores for the next operation interval, and otherwise maintain the first number of active cores for the next operation interval.

15. The system of claim 12 , wherein
the power configuration prediction includes a number of cores to be active in the next operation interval, a number of threads to be active in the next operation interval, and a performance state of the number of cores;
and wherein the power controller is to:
estimate a performance/energy impact of the power configuration prediction;
update at least some of the trained model parameter information for a classified workload type to reduce a performance impact if the estimated performance/energy impact exceeds a first impact threshold; and
update at least some of the trained model parameter information for the classified workload type to increase power savings if the estimated performance/energy impact is less than a second impact threshold.

16. A non-transitory machine-readable medium having stored thereon data, which if used by at least one machine, causes the at least one machine to fabricate at least one integrated circuit to perform a method comprising:
classifying, via a workload classifier, a workload executed on a multicore processor including a plurality of cores, and causing a reduced number of cores of the plurality of cores to be active in a next operation interval based at least in part on the workload classification;
determining an impact of the reduced number of cores on a performance metric of the multicore processor; and
if the impact is greater than a first threshold, updating one or more trained model parameters obtained offline during a machine learning training and stored in a non-volatile storage of the multicore processor during manufacture of the multicore processor, the one or more trained model parameters associated with the workload classifier for a workload type associated with the workload, wherein the updated trained model parameters are to enable a reduction of the impact on the performance metric.

17. The non-transitory machine-readable medium of claim 16 , wherein

Assignees

• Intel Corp

Inventors

• Lee Victor W
• Kim Daehyun
• Bai Yuxin
• Ji Shihao
• Li Sheng
• Kalamkar Dhiraj D
• Mellempudi Naveen K

Classifications

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• G06F1/324 Primary

  by lowering clock frequency · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/5088

  involving task migration · CPC title

• Y02B60/162

  Cross-Sectional Technologies · mapped topic