Systems and methods for cascading radar chips having a low leakage buffer

Patent metadata

Field	Value
Publication number	US-9910133-B2
Application number	US-201514630754-A
Country	US
Kind code	B2
Filing date	Feb 25, 2015
Priority date	Feb 25, 2015
Publication date	Mar 6, 2018
Grant date	Mar 6, 2018

Abstract

A cascaded radar sensor arrangement is disclosed. The arrangement includes a first buffer and a second buffer. The first buffer is within a first radar chip and includes a switch and is configured to mitigate a first leakage signal in the disabled mode. The second buffer is within a second radar chip and has a disabled mode. The second radar chip is cascaded with the first radar chip. A control unit is coupled to the first radar chip and the second radar chip and is configured to set the disabled mode for the first buffer.

First claim

What is claimed is:

1. A cascaded radar sensor arrangement comprising:
a first buffer within a first radar chip and having a disabled mode, wherein the first buffer includes a switch configured to mitigate a first leakage signal in the disabled mode;
a second buffer within a second radar chip and having a disabled mode, wherein the second radar chip is cascaded with the first radar chip; and
a control unit coupled to the first radar chip and the second radar chip and configured to set the disabled mode for the first buffer.

2. The arrangement of claim 1 , wherein the first buffer is configured to block an applied signal from passing as a buffered signal to a power combiner while in the disabled mode.

3. The arrangement of claim 2 , wherein the applied signal is greater than about 1 Volt.

4. The arrangement of claim 1 , wherein the first buffer is part of a first channel configured to generate a first channel signal.

5. The arrangement of claim 1 , wherein the first radar chip includes a transmission channel configured to provide a local oscillator signal.

6. The arrangement of claim 1 , wherein the second buffer is within a transmission channel, wherein the transmission channel receives an external oscillator signal from the first radar chip.

7. The arrangement of claim 1 , wherein the second buffer is within a transmission channel and the transmission channel is configured to generate a channel signal.

8. The arrangement of claim 1 , wherein the first buffer additionally includes a first stage connected to a buffer input of the first buffer and the switch, a matching network connected to the switch, a second stage connected to the switch and a second switch connected to the an output of the second stage.

9. The arrangement of claim 8 , wherein the matching network and the second switch are configured to mitigate the first leakage signal in the disabled mode.

10. The arrangement of claim 8 , wherein the matching network counters a low impedance of the second stage.

11. The arrangement of claim 1 , wherein the switch is configured to short differential lines upon the first buffer being in the disabled mode.

12. The arrangement of claim 1 , further comprising a power distribution circuit configured to provide a first power signal to the first radar chip and a second power signal to the second power chip based on a buffered signal from the first buffer.

13. The arrangement of claim 12 , wherein the buffered signal is a local oscillator (LO) signal.

14. The arrangement of claim 1 , further comprising a power distribution circuit generates a power signal based on a local oscillator signal and provides the power signal to the first radar chip and the second radar chip.

15. The arrangement of claim 1 , wherein the first radar chip is configured to generate a radar signal based on the power signal and the second radar chip passes the power signal as an external signal.

16. The arrangement of claim 1 , further comprising a power distribution circuit and a power combiner, wherein the power combiner is configured to combine a first buffered signal from the first buffer and a second buffered signal from the second buffer into a combined buffered signal and the power distribution circuit is configured to provide a first power signal to the first radar chip and a second power signal to the second power chip based on the combined buffered signal.

Assignees

• Infineon Technologies Ag

Inventors

• Li Hao
• Knapp Herbert

Classifications

• G01S7/032 Primary

  Constructional details for solid-state radar subsystems · CPC title

• G01S13/931

  of land vehicles · CPC title